Digital control of multiphase series capacitor buck converter prototype for the powering of HL-LHC inner triplet magnets

©2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A major upgrade will be conducted in the Large Hardon Collider (LHC) at CERN. This high-luminosity (HL) version of the LHC will increase the nominal luminosity by a factor of five. One of the key technologies of the HL-LHC is the new superconducting inner triplet (IT) magnets, responsible of producing high magnetic fields to focus particle beams. To power the IT magnets from the grid, a multistage power supply with an intermediate 24-V battery pack is being considered. In such topology, a low-voltage high-current dc/dc converter operating with a very high step-down ratio is required for the final conversion stage. In this work, an interleaved multiphase series capacitor buck converter is proposed to feed the IT magnets from the battery pack. A novel voltage regulation approach that ensures the current balance between the paralleled series capacitor cells is also proposed, where one cell is responsible for the output voltage regulation, while the remaining cells are current-regulated. A balanced current sharing between the series capacitor cells is achieved, when the current-controlled cells are referenced by the actual current of the first one. The proposal is theoretically analyzed and experimentally validated in a six-cell 1000-A prototype unit.This work was supported in part by the HL-LHC project by the CERN and APERT (UPV/EHU) “Collaboration in the Study of Power Converter Topologies for Inner Triplet magnets with Energy Recovery in the framework of the High Luminosity upgrade for the LHC at CERN,” in part by the Government of the Basque Country within the fund for research groups of the Basque University system under Grant IT978-16, in part by the Government of Spain through the Agencia Estatal de Investigación under Project DPI2017-85404-P, and in part by the Generalitat de Catalunya under Project 2017 SGR 872.Peer ReviewedPostprint (author's final draft

Input and output total currents characterization in BCM and CCM Interleaved Power Converters Under Inductance Mismatch

This paper presents a complete characterization of input and output currents in interleaved power converters with inductance mismatch, operating in Boundary Conduction Mode (BCM) and Continuous Conduction Mode (CCM). The proposal allows to compute these currents in several interleaved converter topologies for the entire range of operating points, considering any number of phases and any inductance ratio. Input and output currents are recovered from the values obtained when adding the phase currents in the instants where the slopes change; values that are thus defined as key points. This methodology is based on the coincidences that exist between the instants of the phase current key points and those of total currents. By using the computed key points, ripple amplitude, rms value and harmonic content of input and output total currents for the entire range of operating points can be easily obtained. Simulations are conducted on a 5-phase boost converter and a 5-phase buck converter under different conditions in order to validate the proposal expressions. Experimental tests on a 5- phase buck converter are presented under different operation conditions to verify that the proposed method can be applied in real situation.Fil: Cervellini, María Paula. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Carnaghi, Marco. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Antoszczuk, Pablo Daniel. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Garcia Retegui, Rogelio Adrian. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; ArgentinaFil: Funes, Marcos Alan. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Instituto de Investigaciones Científicas y Tecnológicas en Electrónica; Argentin

Fault Tolerant DC–DC Converters at Homes and Offices

The emergence of direct current (DC) microgrids within the context of residential buildings and offices brings in a whole new paradigm in energy distribution. As a result, a set of technical challenges arise, concerning the adoption of efficient, cost-effective, and reliable DC-compatible power conditioning solutions, suitable to interface DC microgrids and energy consuming elements. This thesis encompasses the development of DC–DC power conversion solutions, featuring improved availability and efficiency, suitable to meet the requirements of a comprehensive set of end-uses commonly found in homes and offices. Based on the energy consumption profiles and requirements of the typical elements found at homes and offices, three distinctive groups are established: light-emitting diode (LED) lighting, electric vehicle (EV) charging, and general appliances. For each group, a careful evaluation of the criteria to fulfil is performed, based on which at least one DC–DC power converter is selected and investigated. Totally, a set of five DC–DC converter topologies are addressed in this work, being specific aspects related to fault diagnosis and/or fault tolerance analysed with particular detail in two of them. Firstly, mathematical models are described for LED devices and EV batteries, for the development of a theoretical analysis of the systems’ operation through computational simulations. Based on a compilation of requirements to account for in each end-use (LED lighting, EV charging, and general appliances), brief design considerations are drawn for each converter topology, regarding their architecture and control strategy. Aiming a detailed understanding of the two DC–DC power conversion systems subjected to thorough evaluation in this work – interleaved boost converter and fault-tolerant single-inductor multiple-output (SIMO) converter – under both normal and abnormal conditions, the operation of the systems is evaluated in the presence of open-circuit (OC) faults. Parameters of interest are monitored and evaluated to understand how the failures impact the operation of the entire system. At this stage, valuable information is obtained for the development of fault diagnosis strategies. Taking profit of the data collected in the analysis, a novel fault diagnostic strategy is presented, targeting interleaved DC–DC boost converters for general appliances. Ease of implementation, fast diagnostic and robustness against false alarms distinguish the proposed approach over the state-of-the-art. Its effectiveness is confirmed through a set of operation scenarios, implemented in both simulation environment and experimental context. Finally, an extensive set of reconfiguration strategies is presented and evaluated, aiming to grant fault tolerance capability to the multiple DC–DC converter topologies under analysis. A hybrid reconfiguration approach is developed for the interleaved boost converter. It is demonstrated that the combination of reconfiguration strategies promotes remarkable improvements on the post-fault operation of the converter. In addition, an alternative SIMO converter architecture, featuring inherent tolerance against OC faults, is presented and described. To exploit the OC fault tolerance capability of the fault-tolerant SIMO converter, a converter topology targeted at residential LED lighting systems, two alternative reconfiguration strategies are presented and evaluated in detail. Results obtained from computational simulations and experimental tests confirm the effectiveness of the approaches. To further improve the fault-tolerant SIMO converter with regards to its robustness against sensor faults, while simplifying its hardware architecture, a sensorless current control strategy is presented. The proposed control strategy is evaluated resorting to computational simulations.O surgimento de micro-redes em corrente contínua (CC) em edifícios residenciais e de escritórios estabelece um novo paradigma no domínio da distribuição de energia. Como consequência disso, surge uma panóplia de desafios técnicos ligados à adopção de soluções de conversão de energia, compatíveis com CC, que demonstrem ser eficientes, rentáveis e fiáveis, capazes de estabelecer a interface entre micro-redes em CC e as cargas alimentadas por esse sistema de energia. Até aos dias de hoje, os conversores CC–CC têm vindo a ser maioritariamente utilizados em aplicações de nicho, que geralmente envolvem níveis de potência reduzidos. Porém, as perspectivas futuras apontam para a adopção, em larga escala, destas tecnologias de conversão de energia, também em equipamentos eléctricos residenciais e de escritórios. Tal como qualquer outra tecnologia de conversão electrónica de potência, os conversores CC–CC podem ver o seu funcionamento afectado por falhas que degradam o seu bom funcionamento, sendo que essas falhas acabam por afectar não apenas os conversores em si, mas também as cargas que alimentam, limitando assim o tempo de vida útil do conjunto conversor + carga. Desta forma, é fulcral localizar a origem da falha, para que possam ser adoptadas acções correctivas, capazes de limitar as consequências nefastas associadas à falha. Para responder a este desafio, esta tese contempla o desenvolvimento de soluções de conversão de energia CC–CC altamente eficientes e fiáveis, capazes de responder a requisitos impostos por um conjunto alargado de equipamentos frequentemente encontrados em habitações e escritórios. Com base nos perfis de consumo de energia eléctrica e nos requisitos impostos pelas cargas tipicamente utilizadas em habitações e escritórios, são estabelecidos três grupos distintos: iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral. Para cada grupo, é efectuada uma avaliação cuidadosa dos critérios a respeitar, sendo com base nesses critérios que será escolhida e investigada pelo menos uma topologia de conversor CC–CC. No total, são abordadas cinco topologias de conversores CC–CC distintas, sendo que os aspectos ligados ao diagnóstico de avarias e/ou tolerância a falhas são analisados com particular detalhe em duas dessas topologias. Inicialmente, são estabelecidos modelos matemáticos descritivos do comportamento das principais cargas consideradas no estudo – díodos emissores de luz e baterias de VEs – visando a análise teórica do funcionamento dos sistemas em estudo, suportada por simulações computacionais. Com base numa compilação de requisitos a ter em conta em cada aplicação – iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral – são estabelecidas considerações ligadas à escolha de cada topologia de conversor não isolado, no que respeita à sua arquitectura e estratégia de controlo. Visando o conhecimento aprofundado das duas topologias de conversor CC–CC alvo de particular enfoque neste trabalho – conversor entrelaçado elevador e conversor de entrada única e múltiplas saídas, tolerante a falhas – quer em funcionamento normal, quer em funcionamento em modo de falha, é avaliado o funcionamento de ambas as topologias na presença de falhas de circuito aberto nos semicondutores activos. Para o efeito, são monitorizados e analisados parâmetros úteis à percepção da forma como os modos de falha avaliados neste trabalho impactam o funcionamento de todo o sistema. Nesta fase, é obtida informação fundamental ao desenvolvimento de estratégias de diagnóstico de avarias, particularmente indicadas para avarias de circuito aberto nos semicondutores activos dos conversores em estudo. Com base na informação recolhida anteriormente, é apresentada uma nova estratégia de diagnóstico de avarias direccionada a conversores CC–CC elevadores entrelaçados utilizados em aparelhos eléctricos, em geral. Facilidade de implementação, rapidez e robustez contra falsos positivos são algumas das características que distinguem a estratégia proposta em relação ao estado da arte. A sua efectividade é confirmada com recurso a uma multiplicidade de cenários de funcionamento, implementados quer em ambiente de simulação, quer em contexto experimental. Por fim, é apresentada e avaliada uma gama alargada de estratégias de reconfiguração, que visam assegurar a tolerância a falhas das diversas topologias de conversores CC–CC em estudo. É desenvolvida uma estratégia de reconfiguração híbrida, direccionada ao conversor entrelaçado elevador, que combina múltiplas medidas de reconfiguração mais simples num único procedimento. Demonstra-se que a combinação de múltiplas estratégias de reconfiguração introduz melhorias substanciais no funcionamento do conversor ao longo do período pós-falha, ao mesmo tempo que assegura a manutenção da qualidade da energia à entrada e saída do conversor reconfigurado. Noutra frente, é apresentada e descrita uma arquitectura alternativa do conversor de entrada única e múltiplas saídas, com tolerância a falhas de circuito aberto. Através da configuração proposta, é possível manter o fornecimento de energia eléctrica a todas as saídas do conversor. Para tirar máximo proveito da tolerância a falhas do conversor de entrada única e múltiplas saídas, uma topologia de conversor indicada para sistemas residenciais de iluminação baseados em díodos emissores de luz, são apresentadas e avaliadas duas estratégias de reconfiguração do conversor, exclusivamente baseadas na adaptação do controlo aplicado ao conversor. Os resultados de simulação computacional e os resultados experimentais obtidos confirmam a efectividade das abordagens adoptadas, através da melhoria da qualidade da energia eléctrica fornecida às diversas saídas do conversor. São assim asseguradas condições essenciais ao funcionamento ininterrupto e estável dos sistemas de iluminação, já que a qualidade da energia eléctrica fornecida aos sistemas de iluminação tem impacto directo na qualidade da luz produzida. Por fim, e para aprimorar o conversor de entrada única e múltiplas saídas tolerante a falhas, no que respeita à sua robustez contra falhas em sensores, é apresentada uma estratégia de controlo de corrente que evita o recurso excessivo a sensores e, ao mesmo tempo, simplifica a estrutura de controlo do conversor. A estratégia apresentada é avaliada através de simulações computacionais. A abordagem apresentada assume vantagens em múltiplos domínios, sendo de destacar vantagens como a melhoria da fiabilidade de todo o sistema de iluminação (conversor + carga), os ganhos atingidos ao nível do rendimento, a redução do custo de implementação da solução, ou a simplificação da estrutura de controlo.This work was supported by the Portuguese Foundation for Science and Technology (FCT) under grant number SFRH/BD/131002/2017, co-funded by the Ministry of Science, Technology and Higher Education (MCTES), by the European Social Fund (FSE) through the ‘Programa Operacional Regional Centro’ (POR-Centro), and by the Human Capital Operational Programme (POCH)

Design Approaches to Enhance Power Density in Power Converters for Traction Applications

This dissertation presents a design strategy to increase the power density for automotive Power Conversion Units (PCUs) consisting of DC-DC and DC-AC stages. The strategy significantly improves the volumetric power density, as evident by a proposed PCU constructed and tested having 55.6 kW/L, representing an 11.2 % improvement on the Department of Energy’s 2025 goal of 50 kW/L for the same power electronics architecture. The dissertation begins with a custom magnetic design procedure, based on optimization of a predetermined C-core geometrical relationship and custom Litz wire. It accounts for electrical and thermal tradeoffs to produce a magnetic structure to best accomplish volume and thermal constraints. This work is coupled with a control strategy for the DC-DC converter whereby a variable-frequency Discontinuous Conduction Mode (DCM) control is used to further reduce the required values of the passive components, to provide an increase in power density and a large improvement of low-power-level efficiency, experimentally demonstrated at full power through an 80 kW Interleaved Boost Converter. Integration of this enhanced DC-DC stage to the DC-AC stage requires a DC-Link capacitor, which hinders achieving power density targets. Increasing the switching frequency is an established method of reducing the size of passives. However, it is the RMS current sizing requirements that diminishes any gains achieved by raising the switching frequency. A synchronous carrier phase shift-based control algorithm, that aligns the output current of the boost stage with the input current of an inverter, is proposed to reduce the RMS current in the DC-Link capacitor by up to 25% and an average 20% smaller capacitor volume. Lastly, a new electrothermal platform based on paralleled discrete devices is presented for a 50 kW traction inverter. Embedded capacitors within the vacant volume of the hybrid material thermal management structure enables higher power density (155 kW/L) and significantly reduces cost

Design Approaches to Enhance Power Density in Power Converters for Traction Applications

This dissertation presents a design strategy to increase the power density for automotive Power Conversion Units (PCUs) consisting of DC-DC and DC-AC stages. The strategy significantly improves the volumetric power density, as evident by a proposed PCU constructed and tested having 55.6 kW/L, representing an 11.2 % improvement on the Department of Energy’s 2025 goal of 50 kW/L for the same power electronics architecture. The dissertation begins with a custom magnetic design procedure, based on optimization of a predetermined C-core geometrical relationship and custom Litz wire. It accounts for electrical and thermal tradeoffs to produce a magnetic structure to best accomplish volume and thermal constraints. This work is coupled with a control strategy for the DC-DC converter whereby a variable-frequency Discontinuous Conduction Mode (DCM) control is used to further reduce the required values of the passive components, to provide an increase in power density and a large improvement of low-power-level efficiency, experimentally demonstrated at full power through an 80 kW Interleaved Boost Converter. Integration of this enhanced DC-DC stage to the DC-AC stage requires a DC-Link capacitor, which hinders achieving power density targets. Increasing the switching frequency is an established method of reducing the size of passives. However, it is the RMS current sizing requirements that diminishes any gains achieved by raising the switching frequency. A synchronous carrier phase shift-based control algorithm, that aligns the output current of the boost stage with the input current of an inverter, is proposed to reduce the RMS current in the DC-Link capacitor by up to 25% and an average 20% smaller capacitor volume. Lastly, a new electrothermal platform based on paralleled discrete devices is presented for a 50 kW traction inverter. Embedded capacitors within the vacant volume of the hybrid material thermal management structure enables higher power density (155 kW/L) and significantly reduces cost

The behaviour and analysis of a three-phase AC-DC step-down unity power factor converter

Abstract unavailable please refer to PD

Transient Response Improvement For Multi-phase Voltage Regulators

Next generation microprocessor (Vcore) requirements for high current slew rates and fast transient response together with low output voltage have posed great challenges on voltage regulator (VR) design . Since the debut of Intel 80X86 series, CPUs have greatly improved in performance with a dramatic increase on power consumption. According to the latest Intel VR11 design guidelines , the operational current may ramp up to 140A with typical voltages in the 1.1V to 1.4V range, while the slew rate of the transient current can be as high as 1.9A/ns [1, 2]. Meanwhile, the transient-response requirements are becoming stringer and stringer. This dissertation presents several topics on how to improve transient response for multi-phase voltage regulators. The Adaptive Modulation Control (AMC) is a type of non-linear control method which has proven to be effective in achieving high bandwidth designs as well as stabilizing the control loop during large load transients. It adaptively adjusts control bandwidth by changing the modulation gain, depending on different load conditions. With the AMC, a multiphase voltage regulator can be designed with an aggressively high bandwidth. When in heavy load transients where the loop could be potentially unstable, the bandwidth is lowered. Therefore, the AMC provides an optimal means for robust high-bandwidth design with excellent transient performance. The Error Amplifier Voltage Positioning (EAVP) is proposed to improve transient response by removing undesired spikes and dips after initial transient response. The EAVP works only in a short period of time during transient events without modifying the power stage and changing the control loop gain. It facilitates the error amplifier voltage recovering during transient events, achieving a fast settling time without impact on the whole control loop. Coupled inductors are an emerging topology for computing power supplies as VRs with coupled inductors show dynamic and steady-state advantages over traditional VRs. This dissertation first covers the coupling mechanism in terms of both electrical and reluctance modeling. Since the magnetizing inductance plays an important role in the coupled-inductor operation, a unified State-Space Averaging model is then built for a two-phase coupled-inductor voltage regulator. The DC solutions of the phase currents are derived in order to show the impact of the magnetizing inductance on phase current balancing. A small signal model is obtained based on the state-space-averaging model. The effects of magnetizing inductance on dynamic performance are presented. The limitations of conventional DCR current-sensing for coupled inductors are addressed. Traditional inductor DCR current sensing topology and prior arts fail to extract phase currents for coupled inductors. Two new DCR current sensing topologies for coupled inductors are presented in this dissertation. By implementation of simple RC networks, the proposed topologies can preserve the coupling effect between phases. As a result, accurate phase inductor currents and total current can be sensed, resulting in excellent current and voltage regulation. While coupled-inductor topologies are showing advantages in transient response and are becoming industry practices, they are suffering from low steady-state operating efficiency. Motivated by the challenging transient and efficiency requirements, this dissertation proposes a Full Bridge Coupled Inductor (FBCI) scheme which is able to improve transient response as well as savor high efficiency at (a) steady state. The FBCI can change the circuit configuration under different operational conditions. Its flexible topology is able to optimize both transient response and steady-state efficiency. The flexible core configuration makes implementation easy and clear of IP issues. A novel design methodology for planar magnetics based on numerical analysis of electromagnetic fields is offered and successfully applied to the design of low-voltage high power density dc-dc converters. The design methodology features intense use of FEM simulation. The design issues of planar magnetics, including loss mechanism in copper and core, winding design on PCB, core selections, winding arrangements and so on are first reviewed. After that, FEM simulators are introduced to numerically compute the core loss and winding loss. Consequently, a software platform for magnetics design is established, and optimized magnetics can then be achieved. Dynamic voltage scaling (DVS) technology is a common industry practice in optimizing power consumption of microprocessors by dynamically altering the supply voltage under different operational modes, while maintaining the performance requirements. During DVS operation, it is desirable to position the output voltage to a new level commanded by the microprocessor (CPU) with minimum delay. However, voltage deviation and slow settling time usually exist due to large output capacitance and compensation delay in voltage regulators. Although optimal DVS can be achieved by modifying the output capacitance and compensation, this method is limited by constraints from stringent static and dynamic requirements. In this dissertation, the effects of output capacitance and compensation network on DVS operation are discussed in detail. An active compensator scheme is then proposed to ensure smooth transition of the output voltage without change of power stage and compensation during DVS. Simulation and experimental results are included to demonstrate the effectiveness of the proposed scheme

Soft-Switching Techniques of Power Conversion System in Automotive Chargers

abstract: This thesis investigates different unidirectional topologies for the on-board charger in an electric vehicle and proposes soft-switching solutions in both the AC/DC and DC/DC stage of the converter with a power rating of 3.3 kW. With an overview on different charger topologies and their applicability with respect to the target specification a soft-switching technique to reduce the switching losses of a single phase boost-type PFC is proposed. This work is followed by a modification to the popular soft-switching topology, the dual active bridge (DAB) converter for application requiring unidirectional power flow. The topology named as the semi-dual active bridge (S-DAB) is obtained by replacing the fully active (four switches) bridge on the load side of a DAB by a semi-active (two switches and two diodes) bridge. The operating principles, waveforms in different intervals and expression for power transfer, which differ significantly from the basic DAB topology, are presented in detail. The zero-voltage switching (ZVS) characteristics and requirements are analyzed in detail and compared to those of DAB. A small-signal model of the new configuration is also derived. The analysis and performance of S-DAB are validated through extensive simulation and experimental results from a hardware prototype. Secondly, a low-loss auxiliary circuit for a power factor correction (PFC) circuit to achieve zero voltage transition is also proposed to improve the efficiency and operating frequency of the converter. The high dynamic energy generated in the switching node during turn-on is diverted by providing a parallel path through an auxiliary inductor and a transistor placed across the main inductor. The paper discusses the operating principles, design, and merits of the proposed scheme with hardware validation on a 3.3 kW/ 500 kHz PFC prototype. Modifications to the proposed zero voltage transition (ZVT) circuit is also investigated by implementing two topological variations. Firstly, an integrated magnetic structure is built combining the main inductor and auxiliary inductor in a single core reducing the total footprint of the circuit board. This improvement also reduces the size of the auxiliary capacitor required in the ZVT operation. The second modification redirects the ZVT energy from the input end to the DC link through additional half-bridge circuit and inductor. The half-bridge operating at constant 50% duty cycle simulates a switching leg of the following DC/DC stage of the converter. A hardware prototype of the above-mentioned PFC and DC/DC stage was developed and the operating principles were verified using the same.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Voltage-source-inverters with legs connected in parallel

The number of applications that require the use of power converters has been continually increasing in the last years on account of environmental and economical concerns. The power to be processed by these converters has been growing too. These applications include uninterruptible power supplies, motor drives, and distributed generation, such as solar photo-voltaic panels and wind turbines. The rated power of such converters can be raised by increasing the output currents. This can be chieved by connecting converter, converter legs or power devices in parallel. The connection of legs in parallel in a voltage ource inverter is made by means of inductors, hich can be either magnetically coupled or uncoupled. One of the issues that needs to be addressed is achieving an even contribution to the output current from all the legs. Current imbalances are due to circulating currents among the legs which must be avoided or controlled since they produce additional losses and stress to the power devices of the converter. An efficient technique to attain such a balance is presented in this thesis. The balancing technique achieves the objective regardless of the type of inductors used. In spite of the afore mentioned issues, the potential benefits of paralleling converter legs make their use a worthwhile option. Some of the additional benefits of paralleling are the improvement in the total harmonic distortion of the output current and voltage and the reduction of the output filters. Besides, inverters with legs connected in parallel are modular and because of that, their production and maintenance become less expensive. Moreover, they qualify for the implementation of fault-tolerant techniques thus offering the possibility to achieve systems with improved overall reliability. Interleaving of the carriers can be used to modulate the reference signals for each leg, which leads to a reduction in the output current ripple without resorting to increasing the switching frequency. A whole set of shifted carriers is required if interleaved pulse-width modulators are used. Implementing this by means of a digital signal processor (DSP) means that the higher the number of carriers, the higher the number of DSP timing resources required. Provided that the latter are usually limited, this could be a drawback when increasing the number of interleaved carriers. In this thesis the implementation of a pulse-width modulation (PWM) scheme where all modulators use the same carrier offering the same results as if a set of n interleaved carriers were used is presented. Since the proposed algorithm takes maximum benefit from the PWM units available in a DSP, a higher number of legs connected in parallel can be controlled without adding any external processing hardware. In multiphase voltage source inverters with n interleaved parallel-connected legs, the best single-phase output voltage is achieved when the carriers are evenly phase shifted. However, switching among nonadjacent levels can be observed at regular intervals in the line-to-line voltages, causing bad harmonic performance. This thesis includes a novel implementation of PWM that improves the quality of the line-to-line output voltages in interleaved multiphase voltage-source inverters. With the proposed method, switching in the line-to-line voltages happens exclusively between adjacent levels. The modulator utilizes two sets of n evenly phase-shifted carriers that are dynamically allocated. Because of its generality, the proposed implementation is valid for any number of phases and any number of legs in parallel. All the modulation and control algorithms proposed in this thesis have been firstly simulated on Matlab/Simulink models, and then experimentally corroborated on a low power laboratory prototype.El número de aplicaciones que requiere del uso de convertidores de potencia ha crecido de forma regular en los últimos años debido a cuestiones económicas y ambientales. Entre ellas se incluyen fuentes de alimentación ininterrumpibles, accionamientos de motores y sistemas de generación distribuida, como paneles fotovoltaicos o turbinas eólicas. La potencia nominal de dichos convertidores puede aumentarse incrementando las corrientes de salida. Esto puede lograrse mediante la conexión en paralelo de: semiconductores, ramas de convertidor o convertidores. La conexión en paralelo de las ramas de un inversor con fuente de tensión se efectúa mediante inductancias, que pueden estar magnéticamente acopladas o no. Una de las cuestiones que hay que lograr es una contribución equitativa a la corriente de salida por parte de todas las ramas. Los desequilibrios se deben a las corrientes que circulan entre las ramas y que deben evitarse, o controlarse, pues causan solicitaciones y pérdidas adicionales en los dispositivos de potencia del convertidor. En esta tesis se presenta una técnica eficiente para conseguir dicho equilibrio. Dicha técnica es efectiva independientemente del tipo de bobinas utilizado. A pesar de las cuestiones mencionadas, los beneficios de la conexión de ramas en paralelo las convierte en una opción a considerar. Entre sus beneficios adicionales se encuentran la mejora en la distorsión armónica total de las tensiones y corrientes de salida y la reducción de los filtros de salida. Además, los convertidores con ramas en paralelo son modulares y, de este modo, su producción y mantenimiento resulta más económico. Es más, son ideales para la implantación de técnicas tolerantes a fallos, lo que permite obtener sistemas con una mejor fiabilidad global. Para la modulación de las señales de cada rama pueden utilizarse técnicas de entrelazado de las portadoras, lo que conduce a un menor rizado en la corriente de salida sin tener que recurrir a mayores frecuencias de conmutación. Si se usan moduladores de anchura de pulso entrelazados, se necesita un conjunto de señales portadoras desplazadas. La implantación de esto mediante un procesador digital de señal (DSP) implica que a mayor número de portadoras, mayor será el número de recursos de temporización del DSP que se necesiten. Dado que estos últimos son normalmente limitados, esto podría ser un inconveniente cuando se quiera incrementar el número de portadoras entrelazadas. En esta tesis se presenta la implementación de un esquema de modulación de anchura de pulso (PWM) en el que todos los moduladores usan una misma portadora y que ofrece el mismo resultado que si se utilizara todo un conjunto de portadoras entrelazadas. Como el algoritmo propuesto saca el mejor provecho de las unidades de PWM disponibles en el DSP, se podría controlar un mayor número de ramas en paralelo sin necesidad de ninguna circuitería externa adicional. En inversores con fuente de corriente polifásicos con n ramas conectadas en paralelo, la mejor tensión de fase de salida se obtiene cuando las portadoras están desfasadas por igual. Sin embargo, se observan transiciones entre niveles de salida no adyacentes en las tensiones de línea a intervalos regulares, lo que ocasiona malas prestaciones armónicas. Esta tesis incluye una novedosa implementación de PWM que mejora la calidad de la tensión de línea en inversores con fuente de tensión. Con el método propuesto, las transiciones en las tensiones de línea se producen únicamente entre niveles de tensión adyacentes. El modulador utiliza dos conjuntos de n Portadoras regularmente desfasadas cuyo uso se va asignando de forma dinámica. Dada su formulación genérica, la implementación propuesta es válida para cualquier número de fases y cualquier número de rama