An efficient logic fault diagnosis framework based on effect-cause approach

Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more challenging. In this research, we present an efficient effect-cause diagnosis framework for combinational VLSI circuits. The framework consists of three stages to obtain an accurate and reasonably precise diagnosis. First, an improved critical path tracing algorithm is proposed to identify an initial suspect list by backtracing from faulty primary outputs toward primary inputs. Compared to the traditional critical path tracing approach, our algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to rank the suspects so that the most suspicious one will be ranked at or near the top. Several fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis, fault simulation is performed on the top suspect nets using several common fault models. The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this diagnosis approach is efficient both in terms of memory space and CPU time and the diagnosis results are accurate and reasonably precise

Evaluation of backtracing based diagnosis algorithms

With the growing size and complexity of modern circuits, more algorithms are being developed nowadays for efficient fault diagnosis. Backtracing based diagnosis algorithms are effect-cause approaches that start from the failing outputs of the circuit and try to diagnose fault locations by backtracing lines toward the circuit inputs. In this thesis, general functionality was extracted between backtracing based diagnosis algorithms and implemented as an extension to an existing diagnosis framework. Furthermore, a simple graphical user interface was developed for the extended framework. The extended framework aims at facilitating the implementation and evaluation of different backtracing based diagnosis algorithms. In order to demonstrate its powerfulness, two modern backtracing based diagnosis algorithms were implemented on top of the extended framework. A number of diagnosis experiments on benchmark circuits was carried out in order to evaluate the two implemented algorithms. The experimental tools used and the results obtained are presented

On-line diagnosis of unrestricted faults

A formal model for the study of on-line diagnosis is introduced and used to investigate the diagnosis of unrestricted faults. A fault of a system S is considered to be a transformation of S into another system S' at some time tau. The resulting faulty system is taken to be the system which looks like S up to time tau, and like S' thereafter. Notions of fault tolerance error are defined in terms of the resulting system being able to mimic some desired behavior as specified by a system similar to S. A notion of on-line diagnosis is formulated which involves an external detector and a maximum time delay within which every error caused by a fault in a prescribed set must be detected. It is shown that if a system is on-line diagnosable for the unrestricted set of faults then the detector is at least as complex, in terms of state set size, as the specification. The use of inverse systems for the diagnosis of unrestricted faults is considered. A partial characterization of those inverses which can be used for unrestricted fault diagnosis is obtained

Investigations into the feasibility of an on-line test methodology

This thesis aims to understand how information coding and the protocol that it supports can affect the characteristics of electronic circuits. More specifically, it investigates an on-line test methodology called IFIS (If it Fails It Stops) and its impact on the design, implementation and subsequent characteristics of circuits intended for application specific lC (ASIC) technology. The first study investigates the influences of information coding and protocol on the characteristics of IFIS systems. The second study investigates methods of circuit design applicable to IFIS cells and identifies the· technique possessing the characteristics most suitable for on-line testing. The third study investigates the characteristics of a 'real-life' commercial UART re-engineered using the techniques resulting from the previous two studies. The final study investigates the effects of the halting properties endowed by the protocol on failure diagnosis within IFIS systems. The outcome of this work is an identification and characterisation of the factors that influence behaviour, implementation costs and the ability to test and diagnose IFIS designs

On-line diagnosis of sequential systems, 2

The theory and techniques applicable to the on-line diagnosis of sequential systems, were investigated. A complete model for the study of on-line diagnosis is developed. First an appropriate class of system models is formulated which can serve as a basis for a theoretical study of on-line diagnosis. Then notions of realization, fault, fault-tolerance and diagnosability are formalized which have meaningful interpretations in the the context of on-line diagnosis. The diagnosis of systems which are structurally decomposed and are represented as a network of smaller systems is studied. The fault set considered is the set of faults which only affect one component system is the network. A characterization of those networks which can be diagnosed using a purely combinational detector is achieved. A technique is given which can be used to realize any network by a network which is diagnosable in the above sense. Limits are found on the amount of redundancy involved in any such technique

Learning digital test and diagnostics via Internet

An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access to the hardware equipments, which can be used in the classroom, for learning at home, in laboratory research and training, or for carrying out testing of students during exams. The tools support university courses on digital electronics, computer hardware, testing and design for testability to learn by hands-on exercises how to design digital systems, how to make them testable, how to build self-testing systems, how to generate test patterns, how to analyze the quality of tests, and how to localize faults in hardware. The tasks chosen for hands-on training represent simultaneously research problems, which allow to fostering in students critical thinking, problem solving skills and creativity