Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation. We first describe a deterministic broadside test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same test. To reduce the complexity of test generation, sub-procedures with low complexity are applied before a complete branch-and-bound procedure. Next, we describe a method based on static timing analysis to select critical paths for test generation. Logic conditions that are necessary for detecting a path delay fault are considered to refine the accuracy of static timing analysis, using input necessary assignments. Input necessary assignments are input values that must be assigned to detect a fault. The method calculates more accurate path delays, selects paths that are critical during test application, and identifies undetectable path delay faults. These two methods are applicable to off-line test generation. For large circuits with high complexity and frequency, built-in test generation is a cost-effective method for delay testing. For a circuit that is embedded in a larger design, we developed a method for built-in generation of functional broadside tests to avoid excessive power dissipation during test application and the overtesting of delay faults, taking the functional constraints on the primary input sequences of the circuit into consideration. Functional broadside tests are scan-based two-pattern tests for delay faults that create functional operation conditions during test application. To avoid the potential fault coverage loss due to the exclusive use of functional broadside tests, we also developed an optional DFT method based on state holding to improve fault coverage. High delay fault coverage can be achieved by the developed method for benchmark circuits using simple hardware

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing

Формирование адресных последовательностей с заданной переключательной активностью

The relevance of testing modern computing systems and, first of all, their storage devices is shown. The studies are based on the use of a universal method for generating the address sequences with desired      properties for multiple March tests of random access memory devices.  The modification of economical method of Antonov and Saleev is used as mathematical model to form Sobol sequences. For this model a structural diagram of its hardware implementation is presented, where the storage device for storing direction numbers is used as the basis. The set of multitudes makes up the generating matrix. It is noted that the form of the generating matrix determines the basic properties of the generated sequences. Mathematical expressions are obtained that make it possible to estimate the limiting values of switching activity, both of the sequence itself and of its individual bits. A technique is proposed for the synthesis of generators of address sequences with a given switching activity both of its individual bits and of the sequence as a whole. Examples of the application of the proposed methods are considered. The applicability of the presented results to the synthesis of test sequence generators with a given switching activity for the purpose of testing storage devices and the formation of controlled random test sequences is substantiated. The results of the practical implementation of address sequence generators are presented and their main characteristics are evaluated.Показывается актуальность тестирования современных вычислительных систем, и в первую очередь их запоминающих устройств. Исследования основаны на применении универсального метода генерирования адресных последовательностей с заданными свойствами для многократных маршевых тестов оперативных запоминающих устройств. В качестве математической модели используется модификация экономичного способа Антонова и Салеева для формирования последовательностей Соболя. Для указанной модели приводится структурная схема ее аппаратурной реализации, основу которой составляет запоминающее устройство для хранения направляющих чисел. Множество этих чисел образует порождающую матрицу. Отмечается, что вид порождающей матрицы определяет основные свойства генерируемых последовательностей. Получены математические выражения, позволяющие оценить предельные значения переключательной активности самой последовательности и определенных ее разрядов. Предлагаются методики синтеза генераторов адресной последовательности с заданной переключательной активностью как отдельных ее разрядов, так и последовательности в целом. Рассматриваются примеры использования предлагаемых методик. Обосновывается применимость изложенных результатов для синтеза генераторов тестовых последовательностей с заданной переключательной активностью при тестировании запоминающих устройств и формировании управляемых вероятностных тестовых последовательностей. Приводятся результаты практической реализации генераторов адресных последовательностей и оцениваются их основные характеристики.

Генерирование адресных последовательностей с заданной переключательной активностью и повторяемостью адресов

Решается задача разработки методологии генерирования адресных последовательностей с заданной переключательной активностью и повторяемостью адресов, широко используемых при тестировании современных вычислительных систем. Актуальность данной задачи заключается в том, что основной характеристикой различия для адресных последовательностей является переключательная активность как отдельных битов адресов, так и их последовательностей

Генерирование адресных последовательностей с заданной переключательной активностью и повторяемостью адресов

Objectives. The problem of developing a methodology for generating address sequences with a given switching activity and repeatability of addresses widely used in testing modern computing systems is being solved. The relevance of this problem lies in the fact that the main characteristic of the difference and their effectiveness for address sequences is the switching activity of both individual address bits and their sequences.Methods. Presented results are based on a universal method for generating quasi-random Sobol sequences, which are effectively used to generate targeted test sequences. As an initial mathematical model, a modification of the indicated generation method proposed by Antonov and Saleev is used. The main idea of proposed approach is based on the use of rectangular (m + k) × m generating matrices V of arbitrary rank r to generate address sequences.Results. The main properties of sequences generated in accordance with the new mathematical model are determined. A number of statements are given that substantiate the requirements for generator matrices to ensure the maximum period of generated sequences and the multiplicity of repetition of used addresses. The problem of synthesizing the sequences with given values of switching activity F(A) and F(ai) is solved. It is shown that in order to find a generating matrix for generating such sequences, it is necessary to solve the problem of decomposing an integer into terms. This decomposition represents the value of switching activity in the (m + k)-ary mixed number system, in which the weights of the digits are represented as powers of two from 20 to 2m+k-1, and the values of the digits w(vi) lie in the range from 0 to m+k-1. On the basis of proposed restrictions, the notion of an integer decomposition diagram similar to the Young diagram is introduced, and the operation of its modification is defined.Conclusion. The proposed mathematical model expands the possibilities of generating test address sequences with the required values of switching activity of both test sets and their individual bits. The use of generating matrices of non-maximal rank makes it possible to formalize the method of generating address sequences with even repetition of addresses.Цели. Решается задача разработки методологии генерирования адресных последовательностей с заданной переключательной активностью и повторяемостью адресов, широко используемых при тестировании современных вычислительных систем. Актуальность данной задачи заключается в том, что основной характеристикой различия для адресных последовательностей является переключательная активность как отдельных битов адресов, так и их последовательностей.Методы. Представленные результаты основаны на универсальном методе генерирования квазислучайных последовательностей Соболя, эффективно используемых для формирования адресных тестовых последовательностей. В качестве исходной математической модели используется модификация указанного метода генерирования, предложенная Антоновым и Салеевым. Главная идея подхода, предлагаемого в настоящей работе, основана на применении для генерирования адресных последовательностей прямоугольных (m + k) × m порождающих матриц V произвольного ранга r.Результаты. Определены основные свойства последовательностей, генерируемых в соответствии с новой математической моделью. Приведен ряд утверждений, обосновывающих требования к порождающим матрицам для обеспечения максимального периода формируемых последовательностей и кратности повторяемости используемых в них адресов. Решена задача синтеза последовательностей с заданными величинами переключательной активности F(A) и F(ai). Показано, что для нахождения порождающей матрицы для генерирования таких последовательностей необходимо решить задачу разложения целого числа на слагаемые. Такое разложение представляет собой величину переключательной активности в (m+k)-ичной смешанной системе счисления, в которой веса разрядов представлены в виде степеней двойки от 20 до 2m+k-1, а значения цифр w(vi) лежат в диапазоне от 0 до m+k-1. На основе предлагаемых ограничений введено понятие диаграммы разложения целого числа, аналогичное диаграмме Юнга, и определена операция ее модификации.Заключение. Предложенная математическая модель расширяет возможности генерирования тестовых адресных последовательностей с требуемыми значениями переключательной активности как тестовых наборов, так и их отдельных разрядов. Применение порождающих матриц не максимального ранга дает возможность формализации метода генерирования адресных последовательностей с четным повторением адресов

Proceedings of the Second International Mobile Satellite Conference (IMSC 1990)

Presented here are the proceedings of the Second International Mobile Satellite Conference (IMSC), held June 17-20, 1990 in Ottawa, Canada. Topics covered include future mobile satellite communications concepts, aeronautical applications, modulation and coding, propagation and experimental systems, mobile terminal equipment, network architecture and control, regulatory and policy considerations, vehicle antennas, and speech compression

Engineering evaluations and studies. Volume 2: Exhibit B, part 1

Ku-band communication system analysis, S-band system investigations, payload communication investigations, shuttle/TDRSS and GSTDN compatibility analysis are discussed

Synthesis of Test Sequences with a Given Switching Activity

The relevance of using test sequences with a given switching activity is discussed. As a mathematical model for generating the tests, a modification of the Antonov–Saleev method for generating Sobol sequences is used. It is based on the use of maximum-rank generating matrices the form of which determines the main properties of the sequences. It is shown that the construction of a generating matrix is reduced to the problem of partitioning an integer, and an algorithm for splitting into summands of a given form is proposed. Procedures for modifying the partition of an integer into summands and for modifying the value of switching activity are introduced. Three problems are stated for the synthesis of generators of test sequences with a given switching activity. Examples of using the proposed methods and experimental results are considered

NASA Tech Briefs, October 2007

Topics covered include; Wirelessly Interrogated Position or Displacement Sensors; Ka-Band Radar Terminal Descent Sensor; Metal/Metal Oxide Differential Electrode pH Sensors; Improved Sensing Coils for SQUIDs; Inductive Linear-Position Sensor/Limit-Sensor Units; Hilbert-Curve Fractal Antenna With Radiation- Pattern Diversity; Single-Camera Panoramic-Imaging Systems; Interface Electronic Circuitry for an Electronic Tongue; Inexpensive Clock for Displaying Planetary or Sidereal Time; Efficient Switching Arrangement for (N + 1)/N Redundancy; Lightweight Reflectarray Antenna for 7.115 and 32 GHz; Opto-Electronic Oscillator Using Suppressed Phase Modulation; Alternative Controller for a Fiber-Optic Switch; Strong, Lightweight, Porous Materials; Nanowicks; Lightweight Thermal Protection System for Atmospheric Entry; Rapid and Quiet Drill; Hydrogen Peroxide Concentrator; MMIC Amplifiers for 90 to 130 GHz; Robot Would Climb Steep Terrain; Measuring Dynamic Transfer Functions of Cavitating Pumps; Advanced Resistive Exercise Device; Rapid Engineering of Three-Dimensional, Multicellular Tissues With Polymeric Scaffolds; Resonant Tunneling Spin Pump; Enhancing Spin Filters by Use of Bulk Inversion Asymmetry; Optical Magnetometer Incorporating Photonic Crystals; WGM-Resonator/Tapered-Waveguide White-Light Sensor Optics; Raman-Suppressing Coupling for Optical Parametric Oscillator; CO2-Reduction Primary Cell for Use on Venus; Cold Atom Source Containing Multiple Magneto- Optical Traps; POD Model Reconstruction for Gray-Box Fault Detection; System for Estimating Horizontal Velocity During Descent; Software Framework for Peer Data-Management Services; Autogen Version 2.0; Tracking-Data-Conversion Tool; NASA Enterprise Visual Analysis; Advanced Reference Counting Pointers for Better Performance; C Namelist Facility; and Efficient Mosaicking of Spitzer Space Telescope Images