18 research outputs found

    Inductorless Frequency Synthesizers for Low-Cost Wireless

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    AbstractThe quest for ubiquitous wireless connectivity, drives an increasing demand for compact and efficient means of frequency generation. Conventional synthesizer options, however, generally trade one requirement for the other, achieving either excellent levels of efficiency by leveraging LC-oscillators, or a very compact area by relying on ring-oscillators. This chapter describes a recently introduced class of inductorless frequency synthesizers, based on the periodic realignment of a ring-oscillator, that have the potential to break this tradeoff. After analyzing their jitter-power product, the conditions that ensure optimum performance are derived and a novel digital-to-time converter range-reduction technique is introduced, to enable low-jitter and low-power fractional-N frequency synthesis. A prototype, which implements the proposed design guidelines and techniques, has been fabricated in 65 nm CMOS. It occupies a core area of 0:0275 mm2^{2} 2 and covers the 1:6-to-3:0 GHz range, achieving an absolute rms jitter (integrated from 30 kHz-to-30 MHz) of 397 fs at 2:5 mW power. With a corresponding jitter-power figure-of-merit of −244 dB in the fractional-N mode, the prototype outperforms prior state-of-the-art inductorless frequency synthesizers

    A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

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    High Frequency, High Linearity and Low Noise Digital to Time Converter for Phase Adjustment

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    Nowadays, fast communication systems have become vital for our lifestyle. As a result, the digital PLL fulfils a very important role as frequency synthesizer, demodulator or distributor of clock signals in microprocessors and similar digital circuits. Thus, the correction of the signal using a phase adjust- ment is essential for the good operation of the PLL. In this work, it is proposed a variable slope digital to time converter (DTC), as a programmable delay line, used for the correction of the phase of a digital PLL. The work is focused on the study of the performance of the circuit, through the evaluation of fundamental parameters such as RMS jitter, line- arity, resolution and delay range. Accordingly, it is employed a 4-bit topology using 130 nm MOSFET technology. The in- tended DTC takes advantage of CMOS inverters, due to their simplicity and low noise, and capacitors, for the programmable delay RC network. The DTC functioning is based on the activation of switching transistors to trigger the programmable capacitors, through a code to define the number of capacitors that introduce delay. The circuit is complemented with a simple CMOS inverter as a comparator that triggers when the threshold voltage is attained and an output buffer employed to correct the slopes of the signal. The proposed DTC proposed is a single-ended architecture that achieves 52.50 fs RMS jitter, and the resulting DNL and INL are equivalent to 0.1124 LSB and 0.09773 LSB, respectively. The 4-bit de- lay line has a resolution of 15.2 ps, an area of 0.018 mm2 and a power consumption of 62.8 μW from a 1.2 V low dropout regulator (LDO).Atualmente, os sistemas de comunicação rápida tornaram-se vitais para o nosso estilo de vida. Como resultado, a PLL digital apresenta um papel importante em funções como sintetizador de frequên- cia, demodulador ou distribuidor de sinais de relógio de microprocessadores ou circuitos digitais seme- lhantes. Assim, a correção do sinal utilizando um ajuste de fase é essencial para o bom funcionamento da PLL. Neste trabalho, é proposto um conversor digital para tempo de inclinação de curva variável, como uma linha de atraso programável, utilizada para corrigir a fase de uma PLL digital. Este trabalho é focado no estudo da performance do dispositivo, através da avaliação de parâme- tros fundamentais como RMS jitter, linearidade, resolução e range de atraso. Desta forma, a topologia implementada utiliza 4 bits e tecnologia MOSFET 130 . O conversor digital para tempo é criado utilizando inversores CMOS, que têm as vantagens de apresentar simplicidade e baixo ruído, e condensadores, utilizados para programar a rede de atraso de RC. Este funciona com base na ativação de transístores, empregues como interruptores para acionar os conden- sadores programáveis, através de um código que define o número de condensadores ligados que intro- duzem atraso. O circuito é complementado com um inversor CMOS como comparador que é acionado quando a voltagem de threshold é atingida e um buffer de saída implementado para corrigir a inclinação das curvas. O respetivo conversor apresenta uma arquitetura com uma única saída que é capaz de atingir 52.50 fs RMS jitter, e possuí DNL e INL equivalente a 0.1124 LSB e 0.09773 LSB, respetivamente. A linha de atraso de 4 bits tem uma resolução de 15.2 ps, uma área de 0.018 mm2 e um consumo de potência de 62.8 μW vindo de um regulador de baixa queda de tensão de 1.2 V

    Digital enhancement techniques for fractional-N frequency synthesizers

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    Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB. Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers

    Special Topics in Information Technology

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    This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2019-20 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

    Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors

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    University of Minnesota Ph.D. dissertation.November 2016. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); x, 137 pages.Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V
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