2,170 research outputs found

    Genetic algorithms

    Get PDF
    Genetic algorithms are mathematical, highly parallel, adaptive search procedures (i.e., problem solving methods) based loosely on the processes of natural genetics and Darwinian survival of the fittest. Basic genetic algorithms concepts are introduced, genetic algorithm applications are introduced, and results are presented from a project to develop a software tool that will enable the widespread use of genetic algorithm technology

    Memetic Multilevel Hypergraph Partitioning

    Full text link
    Hypergraph partitioning has a wide range of important applications such as VLSI design or scientific computing. With focus on solution quality, we develop the first multilevel memetic algorithm to tackle the problem. Key components of our contribution are new effective multilevel recombination and mutation operations that provide a large amount of diversity. We perform a wide range of experiments on a benchmark set containing instances from application areas such VLSI, SAT solving, social networks, and scientific computing. Compared to the state-of-the-art hypergraph partitioning tools hMetis, PaToH, and KaHyPar, our new algorithm computes the best result on almost all instances

    Performance Comparison of PSO and Its New Variants in the Context of VLSI Global Routing

    Get PDF
    Substantial reduction of gate delay occurred in recent times owing to radical decrement of transistor size. The interconnect length and delay are accordingly increased owing to the exponential escalation of packaging density with additional transistors being fabricated on the same chip area. The function of VLSI routing that seems to be more defying to the scholars, is categorized in global routing and detailed routing phase. In global routing phase, the prevalent method to lessen the wire length for reducing interconnect delay is to adjust the cost of the Steiner tree, devised by the terminal nodes to be interconnected. Nevertheless, Steiner tree problem is a NP-complete problem in classical graph theory where meta-heuristics might impart beneficial elucidations. Particle swarm optimization (PSO) is a robust algorithm concerning VLSI routing field. This chapter is regarding the proposal of a self-adaptive mechanism for monitoring acceleration coefficient of PSO and evaluating its functionalities with the existing acceleration coefficient controlled PSO in numerous allocation topologies of terminal nodes within definite VLSI layout. The outcomes of PSO variant with constriction factor in context to VLSI route reduction ability and robustness are also inspected. Additionally, a new effort in adapting the PSO with embracement of genetic algorithm is established

    Effective network grid synthesis and optimization for high performance very large scale integration system design

    Get PDF
    制度:新 ; 文部省報告番号:甲2642号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新480

    Variable neighbourhood search for the minimum labelling Steiner tree problem

    Get PDF
    We present a study on heuristic solution approaches to the minimum labelling Steiner tree problem, an NP-hard graph problem related to the minimum labelling spanning tree problem. Given an undirected labelled connected graph, the aim is to find a spanning tree covering a given subset of nodes of the graph, whose edges have the smallest number of distinct labels. Such a model may be used to represent many real world problems in telecommunications and multimodal transportation networks. Several metaheuristics are proposed and evaluated. The approaches are compared to the widely adopted Pilot Method and it is shown that the Variable Neighbourhood Search metaheuristic is the most effective approach to the problem, obtaining high quality solutions in short computational running times

    The Novel Approach of Adaptive Twin Probability for Genetic Algorithm

    Full text link
    The performance of GA is measured and analyzed in terms of its performance parameters against variations in its genetic operators and associated parameters. Since last four decades huge numbers of researchers have been working on the performance of GA and its enhancement. This earlier research work on analyzing the performance of GA enforces the need to further investigate the exploration and exploitation characteristics and observe its impact on the behavior and overall performance of GA. This paper introduces the novel approach of adaptive twin probability associated with the advanced twin operator that enhances the performance of GA. The design of the advanced twin operator is extrapolated from the twin offspring birth due to single ovulation in natural genetic systems as mentioned in the earlier works. The twin probability of this operator is adaptively varied based on the fitness of best individual thereby relieving the GA user from statically defining its value. This novel approach of adaptive twin probability is experimented and tested on the standard benchmark optimization test functions. The experimental results show the increased accuracy in terms of the best individual and reduced convergence time.Comment: 7 pages, International Journal of Advanced Studies in Computer Science and Engineering (IJASCSE), Volume 2, Special Issue 2, 201

    Relaxing Synchronization in Distributed Simulated Annealing

    Get PDF
    Simulated annealing is an attractive, but expensive, heuristic for approximating the solution to combinatorial optimization problems. Since simulated annealing is a general purpose method, it can be applied to the broad range of NP-complete problems such as the traveling salesman problem, graph theory, and cell placement with a careful control of the cooling schedule. Attempts to parallelize simulated annealing, particularly on distributed memory multicomputers, are hampered by the algorithm’s requirement of a globally consistent system state. In a multicomputer, maintaining the global state S involves explicit message traffic and is a critical performance bottleneck. One way to mitigate this bottleneck is to amortize the overhead of these state updates over as many parallel state changes as possible. By using this technique, errors in the actual cost C(S) of a particular state S will be introduced into the annealing process. This dissertation places analytically derived bounds on the cost error in order to assure convergence to the correct result. The resulting parallel Simulated Annealing algorithm dynamically changes the frequency of global updates as a function of the annealing control parameter, i.e. temperature. Implementation results on an Intel iPSC/2 are reported

    VLSI Design

    Get PDF
    This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

    Optimization Design Flow of Integrated Circuits based on Machine Learning Approaches

    Get PDF
    Nowadays, the increased complexity of analog/digital circuits and the extremelly wide range of specifications tend to change how an integrated-circuit designer addresses circuit optimization. A traditional analog engineer likes to use some intuition when designing circuits, as a second step following paper-pencil analysis. However, the numerous parameters that influence the circuit IV in modern transistors do not provide good guesses. Moreover, an optimization based on multiple parameter sweep helps only when the design space is reduced, which is not the case in modern designs. The present thesis, developed at INTEL (in Munich site, Germany), addresses new paradigms of circuit optimization. The proposed work relies on the use of machine learning techniques applied to the design of complex CMOS systems
    corecore