72 research outputs found

    A Novel Iterative Structure for Online Calibration of M-Channel Time-Interleaved ADCs

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    Time-Interleaved Analog-to-Digital Converter (TIADC) Compensation Using Multichannel Filters

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    Published methods that employ a filter bank for compensating the timing and bandwidth mismatches of an M-channel time-interleaved analog-to-digital converter (TIADC) were developed based on the fact that each sub-ADC channel is a downsampled version of the analog input. The output of each sub-ADC is filtered in such a way that, when all the filter outputs are summed, the aliasing components are minimized. If each channel of the filter bank has N coefficients, the optimization of the coefficients requires computing the inverse of an MN times MN matrix if the weighted least squares (WLS) technique is used as the optimization tool. In this paper, we present a multichannel filtering approach for TIADC mismatch compensation. We apply the generalized sampling theorem to directly estimate the ideal output of each sub-ADC using the outputs of all the sub-ADCs. If the WLS technique is used as the optimization tool, the dimension of the matrix to be inversed is N times N. For the same number of coefficients (and also the same spurious component performance given sufficient arithmetic precision), our technique is computationally less complex and more robust than the filter-bank approach. If mixed integer linear programming is used as the optimization tool to produce filters with coefficient values that are integer powers of two, our technique produces a saving in computing resources by a factor of approximately (100.2N(M- 1)/(M-1) in the TIADC filter design.published_or_final_versio

    Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

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    In this work, we rst provide an overviewof the state of the art in mismatch error estimation and correction for time-interleaved analog to digital converters (TI-ADCs). Then, we present a novel pilot-based on-line adaptive timing mismatch error estimation approach for TI-ADCs in the context of an impulse radio ultra wideband (IR-UWB) receiver with correlation-based detection. We introduce the developed method and derive the expressions for both additive white Gaussian noise (AWGN) and Rayleigh multipath fading (RMPF) channels. We also derive a lower bound on the required ADC resolution to attain a certainestimation precision. Simulations show the effectiveness of the technique when combined with an adequate compensator. We analyze the estimation error behavior as a function of signal to noise ratio (SNR) and investigate the ADC performance before and after compensation. While all mismatches combined cause the effective number of bits (ENOB) to drop to 3 bits and to 6 bits when considering only timing mismatch, estimation and correction of these errors with the proposed technique can restore a close to ideal behavior.We also show the performance loss at the receiver in terms of bit error rate (BER) and how compensation is able to signicantly improve performance.Fil: Schmidt, Christian Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Figueroa, Jose Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Cousseau, Juan Edmundo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Lopez Tonellotto, Mariana Andrea. University Of Klagenfurt; Austri

    Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

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    4openopenSchmidt C.A.; Figueroa J.L.; Cousseau J.E.; Tonello A.M.Schmidt, C. A.; Figueroa, J. L.; Cousseau, J. E.; Tonello, A. M

    Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

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    Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 19.27 dB and 35.2 dB, respectively. This analysis was done for an input signal frequency of 0.09fs. In the case of an input signal frequency of 0.45fs, an improvement by 33.06 dB and 43.14 dB is respectively achieved in SNDR and SFDR. In addition to the simulation, the algorithm was implemented in hardware for real-time evaluation. The low computational burden of the algorithm allowed an FPGA implementation with a low logic resource usage and a high system clock speed (926.95 MHz for four channel algorithm implementation). Thus, the proposed architecture can be used as a post-processing algorithm in host processors for data acquisition systems to improve the performance of TIADC

    Time-Interleaved Analog-to-Digital-Converters: Modeling, Blind Identification and Digital Correction of Frequency Response Mismatches

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    Analog-to-digital-conversion enables utilization of digital signal processing (DSP) in many applications today such as wireless communication, radar and electronic warfare. DSP is the favored choice for processing information over analog signal processing (ASP) because it can typically offer more ïŹ‚exibility, computational power, reproducibility, speed and accuracy when processing and extracting information. Software deïŹned radio (SDR) receiver is one clear example of this, where radio frequency waveforms are converted into digital form as close to the antenna as possible and all the processing of the information contained in the received signal is extracted in a conïŹgurable manner using DSP. In order to achieve such goals, the information collected from the real world signals, which are commonly analog in their nature, must be converted into digital form before it can be processed using DSP in the respective systems. The common trend in these systems is to not only process ever larger bandwidths of data but also to process data in digital format at ever higher processing speeds with sufficient conversion accuracy. So the analog-to-digital-converter (ADC), which converts real world analog waveforms into digital form, is one of the most important cornerstones in these systems.The ADC must perform data conversion at higher and higher rates and digitize ever-increasing bandwidths of data. In accordance with the Nyquist-Shannon theorem, the conversion rate of the ADC must be suffcient to accomodate the BW of the signal to be digitized, in order to avoid aliasing. The conversion rate of the ADC can in general be increased by using parallel ADCs with each ADC performing the sampling at mutually different points in time. Interleaving the outputs of each of the individual ADCs provides then a higher digitization output rate. Such ADCs are referred to as TI-ADC. However, the mismatches between the ADCs cause unwanted spurious artifacts in the TI-ADC’s spectrum, ultimately leading to a loss in accuracy in the TI-ADC compared to the individual ADCs. Therefore, the removal or correction of these unwanted spurious artifacts is essential in having a high performance TI-ADC system.In order to remove the unwanted interleaving artifacts, a model that describes the behavior of the spurious distortion products is of the utmost importance as it can then facilitate the development of efficient digital post-processing schemes. One major contribution of this thesis consists of the novel and comprehensive modeling of the spurious interleaving mismatches in different TI-ADC scenarios. This novel and comprehensive modeling is then utilized in developing digital estimation and correction methods to remove the mismatch induced spurious artifacts in the TI-ADC’s spectrum and recovering its lost accuracy. Novel and ïŹrst of its kind digital estimation and correction methods are developed and tested to suppress the frequency dependent mismatch spurs found in the TI-ADCs. The developed methods, in terms of the estimation of the unknown mismatches, build on statistical I/Q signal processing principles, applicable without speciïŹcally tailored calibration signals or waveforms. Techniques to increase the analog BW of the ADC are also analyzed and novel solutions are presented. The interesting combination of utilizing I/Q downconversion in conjunction with TI-ADC is examined, which not only extends the TI-ADC’s analog BW but also provides ïŹ‚exibility in accessing the radio spectrum. Unwanted spurious components created during the ADC’s bandwidth extension process are also analyzed and digital correction methods are developed to remove these spurs from the spectrum. The developed correction techniques for the removal of the undesired interleaving mismatch artifacts are validated and tested using various HW platforms, with up to 1 GHz instantaneous bandwidth. Comprehensive test scenarios are created using measurement data obtained from HW platforms, which are used to test and evaluate the performance of the developed interleaving mismatch estimation and correction schemes, evidencing excellent performance in all studied scenarios. The ïŹndings and results presented in this thesis contribute towards increasing the analog BW and conversion rate of ADC systems without losing conversion accuracy. Overall, these developments pave the way towards fulïŹlling the ever growing demands on the ADCs in terms of higher conversion BW, accuracy and speed

    New iterative framework for frequency response mismatch correction in time-interleaved ADCs: Design and performance analysis

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    This paper proposes a new iterative framework for the correction of frequency response mismatch in time-interleaved analog-to-digital converters. Based on a general time-varying linear system model for the mismatch, we treat the reconstruction problem as a linear inverse problem and establish a flexible iterative framework for practical implementation. It encumbrances a number of efficient iterative correction algorithms and simplifies their design, implementation, and performance analysis. In particular, an efficient Gauss-Seidel iteration is studied in detail to illustrate how the correction problem can be solved iteratively and how the proposed structure can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. We also study important issues, such as the sufficient convergence condition and reconstructed signal spectrum, derive new lower bound of signal-to-distortion-and-noise ratio in order to ensure stable operation, and predict the performance of the proposed structure. Furthermore, we propose an extended iterative structure, which is able to cope with systems involving more than one type of mismatches. Finally, the theoretical results and the effectiveness of the proposed approach are validated by means of computer simulations. © 2011 IEEE.published_or_final_versio

    FPGA Implementation of Channel Mismatch Calibration in TIADCs for Signals in Any Nyquist Bands

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    This paper presents a fully digital background calibration technique of the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converters for the wideband bandlimited input signal at any Nyquist bands. The proposed technique does not require an additional reference channel nor a pilot input. The channel mismatch parameters are estimated based on the mismatch frequency band. The experimental results shows the efficiency of the proposed mitigation technique with the SNDR improvement of 16dB for 4-channel 60dB SNR TIADC clocked at 2.7GHz given a multi-tone input occupied at the third Nyquist band. The hardware architecture of the proposed technique is designed and validated on Altera FPGA DE4 board. The synthesized design utilizes a very little amount of the hardware resource in the FPGA chip and works correctly on a Hardware-In-the-Loop emulation framework
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