EMULATION TOOL FOR TESTING FAULT TOLERANCE

The aim of this paper is to show a possible adaptation of the well known microprocessor emulation method for testing fault tolerance, and to examine the advantages of the adap-tation. First a survey on test methods and their application will be given with respect to the possibilities for testing fault tolerant architectures. It will be followed by a short overview of different microprocessor fault models, and the fault injection routines based on the fault models. The injection routines require some hardware extension of the con-ventional microprocessor in-circuit emulator. The necessary extensions are shown on a MC68000 based in-circuit emulator. Finally, some improvement possibilities are discussed

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead

Special Session on Industry 4.0

No abstract available

Wireless Sensor Networks (WSN): An Overview

The plethora of research and development efforts on Wireless Sensor Networks is an indication that the technology has emerged an active research area in recent times. In this paper, a review of this intelligent technology is undertaken. Its working mechanisms, merits, challenges, transmission technologies, simulating tools and applications are considered. The paper concludes with a clear conviction that a sound knowledge of the basics of this technology is a sine qua non to research and development of the technology

Real time embedded software system on a heterogeneous Digital Signal Processor and RISC processor architecture

International audienceThis paper discusses a generic telematics systems based on the OMAPTM (open multimedia application platform)heterogeneous ARMTM/DSP multiprocessor system. These 2 processors are integrated as SOC (system on chip)with a peripheral mix dedicated to the automotive requirements as a one chip solution. These processors are ableto run parallel various real time applications optimized either for the DSP or the ARM-RISC processor or sharedbetween both processors

Intelligent Embedded Software: New Perspectives and Challenges

Intelligent embedded systems (IES) represent a novel and promising generation of embedded systems (ES). IES have the capacity of reasoning about their external environments and adapt their behavior accordingly. Such systems are situated in the intersection of two different branches that are the embedded computing and the intelligent computing. On the other hand, intelligent embedded software (IESo) is becoming a large part of the engineering cost of intelligent embedded systems. IESo can include some artificial intelligence (AI)-based systems such as expert systems, neural networks and other sophisticated artificial intelligence (AI) models to guarantee some important characteristics such as self-learning, self-optimizing and self-repairing. Despite the widespread of such systems, some design challenging issues are arising. Designing a resource-constrained software and at the same time intelligent is not a trivial task especially in a real-time context. To deal with this dilemma, embedded system researchers have profited from the progress in semiconductor technology to develop specific hardware to support well AI models and render the integration of AI with the embedded world a reality

Linux OS emulator and an application binary loader for a high performance microarchitecture simulator

Simulation is a critical step in the development of state of the art microprocessors. Accurate simulation allows designers to confidently investigate various designs, while fast simulation times allow designers to thoroughly explore a design space. RITSim is an endeavor to create a high accuracy, high quality microarchitecture simulation infrastructure. This simulation infrastructure will be available for academic research in low power and high performance computer systems. The scope of this work is to provide a Linux OS Emulator, a Binary Application Loader, and a Linux kernel running in a virtual environment for the RITSim project. In order to evaluate standard software loads and benchmark suites on target microarchitectures simulators must provide support for operating system calls. This may be accomplished with various levels of accuracy. Many past simulators chose to sacrifice simulation accuracy to improve simulation time, while others sacrificed portability and execution time for high accuracy results. This work provides three key elements to the RITSim environment in an effort to create a simulation environment that seamlessly combines both approaches to provide a single integrated tool that allows researchers to choose the approach that is best suited to their needs. A first order simulation mode is provided that makes use of emulated system calls that are executed on the host computer?s operating system to provide quick simulation times. This mode also maintains a high level of portability since the host operating system is used to access the hardware. A high accuracy mode is also available that runs in a highly detailed simulated operating system. When running in the high accuracy mode the simulated operating system must be loaded into a virtual environment allowing the actual instructions of the operating system code to be simulated. Another key element is the binary application loader. This is required by the simulator to load executables into the simulator?s virtual memory space and to prepare it for execution. This involves not only mapping or copying the executable into simulated virtual memory, but also the creation and initialization of a new user mode stack and configuration of the simulated processor?s user mode registers

Aerospace Applications of Microprocessors

An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed

External Verification of SCADA System Embedded Controller Firmware

Critical infrastructures such as oil and gas pipelines, the electric power grid, and railways, rely on the proper operation of supervisory control and data acquisition (SCADA) systems. Current SCADA systems, however, do not have sufficient tailored electronic security solutions. Solutions available are developed primarily for information technology (IT) systems. Indeed, the toolkit for SCADA incident prevention and response is unavailing as the operating parameters associated with SCADA systems are different from IT systems. The unique environment necessitates tailored solutions. Consider the programmable logic controllers (PLCs) that directly connect to end physical systems for control and monitoring of operating parameters -- the compromise of a PLC could result in devastating physical consequences. Yet PLCs remain particularly vulnerable due to a lack of firmware auditing capabilities. This research presents a tool we developed specifically for the SCADA environment to verify PLC firmware. The tool does not require any modifications to the SCADA system and can be implemented on a variety of systems and platforms. The tool captures serial data during firmware uploads and then verifies them against a known good firmware baseline. Attempts to inject modified and/or malicious firmware are identified by the tool. Additionally, the tool can replay and analyze captured data by emulating a PLC during firmware upload. The emulation capability enables verification of the firmware upload from an interface computer without requiring modifications to or interactions with the operational SCADA system. The ability to isolate the tool from production systems and verify the validity of firmware makes the tool a viable application for SCADA incident response teams and security engineers