Integrated temperature sensors in deep sub-micron CMOS technologies

textIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Electrical and Computer Engineerin

A Self-Calibrated Power Detector and Current Sensor for Use in a Power Amplifier Control Circuit

The power amplifier in a transmitter, especially high-power transmitters, generally uses more power than any other component in the signal chain. As a result, large power savings can be achieved if the efficiency of the power amplifier is optimized. Additionally, power amplifiers in high-power transmitters generally experience substantial amounts of reliability-reducing stress such as high temperature operation. Given these considerations, a power amplifier control loop is proposed which will calculate various parameters of the amplifier, such as the power-added efficiency. This control loop will then adjust the input power and DC bias current of the power amplifier to maximize the efficiency while also ensuing the amplifier is not placed in a situation where its reliability is compromised. This thesis will discuss the design of two major blocks that are required in this control loop: a DC bias current sensor and a power detector. The DC bias current sensor must accurately measure the DC bias of the power amplifier since this current is used to calculate the DC power dissipation for the power-added efficiency. In order to ensure the DC current sensor’s output is accurate over a wide temperature range, a reference current calibration scheme is introduced. The fabricated current sensor is able to achieve a measurement accuracy of +/-1% over a current range from 100mA to 4A. The power detector must measure the input and output power of the power amplifier since the power added efficiency takes into account the gain of the amplifier. The proposed power detector utilizes an on-chip reference generator in order to calibrate the peak detector used and provide an accurate and absolute power level. The simulated power detector is able to provide an accuracy of +/-0.5dB over a dynamic range of 40dB. These two designs will be incorporated in the overall power amplifier control system in future work

Design and implementation of a multi-modal sensor with on-chip security

With the advancement of technology, wearable devices for fitness tracking, patient monitoring, diagnosis, and disease prevention are finding ways to be woven into modern world reality. CMOS sensors are known to be compact, with low power consumption, making them an inseparable part of wireless medical applications and Internet of Things (IoT). Digital/semi-digital output, by the translation of transmitting data into the frequency domain, takes advantages of both the analog and digital world. However, one of the most critical measures of communication, security, is ignored and not considered for fabrication of an integrated chip. With the advancement of Moore\u27s law and the possibility of having a higher number of transistors and more complex circuits, the feasibility of having on-chip security measures is drawing more attention. One of the fundamental means of secure communication is real-time encryption. Encryption/ciphering occurs when we encode a signal or data, and prevents unauthorized parties from reading or understanding this information. Encryption is the process of transmitting sensitive data securely and with privacy. This measure of security is essential since in biomedical devices, the attacker/hacker can endanger users of IoT or wearable sensors (e.g. attacks at implanted biosensors can cause fatal harm to the user). This work develops 1) A low power and compact multi-modal sensor that can measure temperature and impedance with a quasi-digital output and 2) a low power on-chip signal cipher for real-time data transfer

Silicon carbide technology for extreme environments

PhD ThesisWith mankind’s ever increasing curiosity to explore the unknown, including a variety of hostile environments where we cannot tread, there exists a need for machines to do work on our behalf. For applications in the most extreme environments and applications silicon based electronics cannot function, and there is a requirement for circuits and sensors to be built from wide band gap materials capable of operation in these domains. This work addresses the initial development of silicon carbide circuits to monitor conditions and transmit information from such hostile environments. The characterisation, simulation and implementation of silicon carbide based circuits utilising proprietary high temperature passives is explored. Silicon carbide is a wide band gap semiconductor material with highly suitable properties for high-power, high frequency and high temperature applications. The bandgap varies depending on polytype, but the most commonly used polytype 4H, has a value of 3.265 eV at room temperature, which reduces as the thermal ionization of electrons from the valence band to the conduction band increases, allowing operation in ambient up to 600°C. Whilst silicon carbide allows for the growth of a native oxide, the quality has limitations and therefore junction field effect transistors (JFETs) have been utilised as the switch in this work. The characteristics of JFET devices are similar to those of early thermionic valve technology and their use in circuits is well known. In conjunction with JFETs, Schottky barrier diodes (SBDs) have been used as both varactors and rectifiers. Simulation models for high temperature components have been created through their characterisation of their electrical parameters at elevated temperatures. The JFETs were characterised at temperatures up to 573K, and values for TO V , β , λ , IS , RS and junction capacitances were extracted and then used to mathematically describe the operation of circuits using SPICE. The transconductance of SiC JFETs at high temperatures has been shown to decrease quadratically indicating a strong dependence upon carrier mobility in the channel. The channel resistance also decreased quadratically as a direct result of both electric field and temperature enhanced trap emission. The JFETs were tested to be operational up to 775K, where they failed due to delamination of an external passivation layer. ii Schottky diodes were characterised up to 573K, across the temperature range and values for ideality factor, capacitance, series resistance and forward voltage drop were extracted to mathematically model the devices. The series resistance of a SiC SBD exhibited a quadratic relationship with temperature indicating that it is dominated by optical phonon scattering of charge carriers. The observed deviation from a temperature independent ideality factor is due to the recombination of carriers in the depletion region affected by both traps and the formation of an interfacial layer at the SiC/metal interface. To compliment the silicon carbide active devices utilised in this work, high temperature passive devices and packaging/circuit boards were developed. Both HfO2 and AlN materials were investigated for use as potential high temperature capacitor dielectrics in metal-insulator-metal (MIM) capacitor structures. The different thicknesses of HfO2 (60nm and 90nm) and 300nm for AlN and the relevance to fabrication techniques are examined and their effective capacitor behaviour at high temperature explored. The HfO2 based capacitor structures exhibited high levels of leakage current at temperatures above 100°C. Along with elevated leakage when subjected to higher electric fields. This current leakage is due to the thin dielectric and high defect density and essentially turns the capacitors into high value resistors in the order of MΩ. This renders the devices unsuitable as capacitors in hostile environments at the scales tested. To address this issue AlN capacitors with a greater dielectric film thickness were fabricated with reduced leakage currents in comparison even at an electric field of 50MV/cm at 600K. The work demonstrated the world’s first high temperature wireless sensor node powered using energy harvesting technology, capable of operation at 573K. The module demonstrated the world’s first amplitude modulation (AM) and frequency modulation (FM) communication techniques at high temperature. It also demonstrated a novel high temperature self oscillating boost converter cable of boosting voltages from a thermoelectric generator also operating at this temperature. The AM oscillator operated at a maximum temperature of 553K and at a frequency of 19.4MHz with a signal amplitude 65dB above background noise. Realised from JFETs and HfO2 capacitors, modulation of the output signal was achieved by varying the load resistance by use of a second SiC JFET. By applying a negative signal voltage of between -2.5 and -3V, a 50% reduction in the signal amplitude and therefore Amplitude Modulation was achieved by modulating the power within the oscillator through the use of this secondary JFET. Temperature drift in the characteristics were also observed, iii with a decrease in oscillation frequency of almost 200 kHz when the temperature changed from 300K to 573K. This decrease is due to the increase in capacitance density of the HfO2 MIM capacitors and increasing junction capacitances of the JFET used as the amplifier within the oscillator circuit. Direct frequency modulation of a SiC Voltage Controlled Oscillator was demonstrated at a temperature of 573K with a oscillation frequency of 17MHz. Realised from an SiC JFET, AlN capacitors and a SiC SBD used as a varactor. It was possible to vary the frequency of oscillations by 100 kHz with an input signal no greater than 1.5V being applied to the SiC SBD. The effects of temperature drift were more dramatic in comparison to the AM circuit at 400 kHz over the entire temperature range, a result of the properties of the AlN film which causes the capacitors to increase in capacitance density by 10%. A novel self oscillating boost converter was commissioned using a counter wound transformer on high temperature ferrite, a SiC JFET and a SiC SBD. Based upon the operation of a free running blocking oscillator, oscillatory behaviour is a result of the electric and magnetic variations in the winding of the transformer and the amplification characteristics of a JFET. It demonstrated the ability to boost an input voltage of 1.3 volts to 3.9 volts at 573K and exhibited an efficiency of 30% at room temperature. The frequency of operation was highly dependent upon the input voltage due to the increased current flow through the primary coil portion of the transformer and the ambient temperature causing an increase in permeability of the ferrite, thus altering the inductance of both primary and secondary windings. However due its simplicity and its ability to boost the input voltage by 250% meant it was capable of powering the transmitters and in conjunction with a Themoelectric Generator so formed the basis for a self powered high temperature silicon carbide sensor node. The demonstration of these high temperature circuits provide the initial stages of being able to produce a high temperature wireless sensor node capable of operation in hostile environments. Utilising the self oscillating boost converter and a high temperature Thermoelectric Generator these prototype circuits were showed the ability to harvest energy from the high temperature ambient and power the silicon carbide circuitry. Along with appropriate sensor technology it demonstrated the feasibility of being able to monitor and transmit information from hazardous locations which is currently unachievable

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches

Ultra low power circuits for a miniature apnoea detection device

Imperial Users onl

Integrated temperature sensor bipolar core

Cílem této práce je popsat možné způsoby realizace teplotního senzoru na křemíkovém čipu v běžných CMOS výrobních technologiích a představit konkrétní implementaci analogového jádra teplotního senzoru využívajícího bipolární tranzistory ve výrobní technologii TSMC 110. Techniky jako chopping, dynamic element matching nebo trimování byly použity k navržení obvodů, jejichž simulovaná 3 přesnost měření je ±3.5 °C bez trimování nebo ±0.6 °C s po jedné trimovací operaci napříč vojenským teplotním rozsahem. Navržené obvody zabírají pouze 0.012 mm čtverečních plochy čipu a jejich celkové parametry jsou srovnatelné s výsledky současných publikovaných prací.The aim of this thesis is to describe the main possible ways of implementing a smart temperature sensor on a silicon chip in common CMOS process technologies and to design an analog front-end of a bipolar transistor based smart temperature sensor in TSMC 110 process technology. Techniques such as chopping, dynamic element matching or trimming have been utilized to design circuits whose simulated 3 measurement precision is ±3.5 °C untrimmed or ±0.6 °C after single point trim over the military temperature range. The designed circuits occupy as little as 0.012 mm squared of die area and their overall performance is comparable to the current state of the art.

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Design and Implementation of Signal Processing Circuitry for Implantable Sensors

Recent technological advancements in integrated circuits and medical technology have made real-time monitoring of physiological factors possible. One such important physiological factor to be measured is glucose. Continuous monitoring of glucose is extremely important for patients with diabetes as it helps make optimal treatment decisions. To enable continuous measurement, a chip containing the sensors and the electronic circuitry is implanted in the human body. This implanted chip provides for continuous measurement and helps reduce inconvenience caused to diabetic patients. A potentiostat forms an integral part of a sensor signal processing circuit. In this thesis the design and simulation of an on-chip potentiostat circuit has been presented. A potentiostat is needed to maintain a constant potential, so that the sensor can measure glucose. This design has been fabricated using a 0.35-m bulk CMOS process available through MOSIS