An ASIC Array Architecture for the DITPOS Algorithm

this paper we have considered the systematic design of a bit-serial ASIC array architecture for DITPOS. It has been shown that the heterogeneous DITPOS, involving a number of subalgorithms, can be mapped onto a regular array meeting practical I/O scheme and timing requirements. The area consumption of the array is estimated at 125 m

A VLSI processor for computing Linear and Circular CORDIC

This report consider the generalised CORDIC algorithm from a theoretical point of view, involving principles, applications and range of convergence. Further is considered the derivation of an instance of this algorithm, allowing computations in circular and linear modes, denoted LCC. Since LCC is intended for use as a BCU in an ASIC VLSI implementation of the DITPOS algorithm, the specifications for LCC has been derived from this application, although it may find application in other designs as well, provided the numerical needs match the one offered by LCC. Also, the derivation of a highly pipelined array architecture with high resource utilisation is treated in detail. The architecture is based upon bit-serial arithmetic, and a physical implementation of a prototype for this architecture is included. The implementation is based on the SOLO 1400 standard cell tool