Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

A Novel Power-Efficient Wireless Multi-channel Recording System for the Telemonitoring of Electroencephalography (EEG)

This research introduces the development of a novel EEG recording system that is modular, batteryless, and wireless (untethered) with the supporting theoretical foundation in wireless communications and related design elements and circuitry. Its modular construct overcomes the EEG scaling problem and makes it easier for reconfiguring the hardware design in terms of the number and placement of electrodes and type of standard EEG system contemplated for use. In this development, portability, lightweight, and applicability to other clinical applications that rely on EEG data are sought. Due to printer tolerance, the 3D printed cap consists of 61 electrode placements. This recording capacity can however extend from 21 (as in the international 10-20 systems) up to 61 EEG channels at sample rates ranging from 250 to 1000 Hz and the transfer of the raw EEG signal using a standard allocated frequency as a data carrier. The main objectives of this dissertation are to (1) eliminate the need for heavy mounted batteries, (2) overcome the requirement for bulky power systems, and (3) avoid the use of data cables to untether the EEG system from the subject for a more practical and less restrictive setting. Unpredictability and temporal variations of the EEG input make developing a battery-free and cable-free EEG reading device challenging. Professional high-quality and high-resolution analog front ends are required to capture non-stationary EEG signals at microvolt levels. The primary components of the proposed setup are the wireless power transmission unit, which consists of a power amplifier, highly efficient resonant-inductive link, rectification, regulation, and power management units, as well as the analog front end, which consists of an analog to digital converter, pre-amplification unit, filtering unit, host microprocessor, and the wireless communication unit. These must all be compatible with the rest of the system and must use the least amount of power possible while minimizing the presence of noise and the attenuation of the recorded signal A highly efficient resonant-inductive coupling link is developed to decrease power transmission dissipation. Magnetized materials were utilized to steer electromagnetic flux and decrease route and medium loss while transmitting the required energy with low dissipation. Signal pre-amplification is handled by the front-end active electrodes. Standard bio-amplifier design approaches are combined to accomplish this purpose, and a thorough investigation of the optimum ADC, microcontroller, and transceiver units has been carried out. We can minimize overall system weight and power consumption by employing battery-less and cable-free EEG readout system designs, consequently giving patients more comfort and freedom of movement. Similarly, the solutions are designed to match the performance of medical-grade equipment. The captured electrical impulses using the proposed setup can be stored for various uses, including classification, prediction, 3D source localization, and for monitoring and diagnosing different brain disorders. All the proposed designs and supporting mathematical derivations were validated through empirical and software-simulated experiments. Many of the proposed designs, including the 3D head cap, the wireless power transmission unit, and the pre-amplification unit, are already fabricated, and the schematic circuits and simulation results were based on Spice, Altium, and high-frequency structure simulator (HFSS) software. The fully integrated head cap to be fabricated would require embedding the active electrodes into the 3D headset and applying current technological advances to miniaturize some of the design elements developed in this dissertation

270 nm Ultra-Thin Self-Adhesive Conformable and Long-Term Air-Stable Complimentary Organic Transistors and Amplifiers

Lightweight, flexible, and conformal bioelectronics are essential for wearable technologies. This paper introduces 270 nm thin organic electronics amplifying circuits that are self-adhesive, skin conformal, and long-term air-stable. This report studies the effect of total device thickness, namely 3 μm and 270 nm devices, on the characterization of organic devices before and after buckling, the longevity of organic field-effect transistors (OFETs) over 5 years, and the lamination of OFETs on the human skin. A single-stage organic complementary inverter and a pseudo-complementary amplifier are fabricated to compare their electrical characteristics, with amplification gains of 10 and 64, respectively. Finally, the study demonstrates a five-stage organic complementary inverter can successfully amplify artificial electromyogram and electrocardiogram signals with gains of 1000 and 1088, respectively

Advanced Interfaces for HMI in Hand Gesture Recognition

The present thesis investigates techniques and technologies for high quality Human Machine Interfaces (HMI) in biomedical applications. Starting from a literature review and considering market SoA in this field, the thesis explores advanced sensor interfaces, wearable computing and machine learning techniques for embedded resource-constrained systems. The research starts from the design and implementation of a real-time control system for a multifinger hand prosthesis based on pattern recognition algorithms. This system is capable to control an artificial hand using a natural gesture interface, considering the challenges related to the trade-off between responsiveness, accuracy and light computation. Furthermore, the thesis addresses the challenges related to the design of a scalable and versatile system for gesture recognition with the integration of a novel sensor interface for wearable medical and consumer application

Wearable, low-power CMOS ISFETs and compensation circuits for on-body sweat analysis

Complementary metal-oxide-semiconductor (CMOS) technology has been a key driver behind the trend of reduced power consumption and increased integration of electronics in consumer devices and sensors. In the late 1990s, the integration of ion-sensitive field-effect transistors (ISFETs) into unmodified CMOS helped to create advancements in lab-on-chip technology through highly parallelised and low-cost designs. Using CMOS techniques to reduce power and size in chemical sensing applications has already aided the realisation of portable, battery-powered analysis platforms, however the possibility of integrating these sensors into wearable devices has until recently remained unexplored. This thesis investigates the use of CMOS ISFETs as wearable electrochemical sensors, specifically for on-body sweat analysis. The investigation begins by evaluating the ISFET sensor for wearable applications, identifying the key advantages and challenges that arise in this pursuit. A key requirement for wearable devices is a low power consumption, to enable a suitable operational life and small form factor. From this perspective, ISFETs are investigated for low power operation, to determine the limitations when trying to push down the consumption of individual sensors. Batteryless ISFET operation is explored through the design and implementation of a 0.35 \si{\micro\metre} CMOS ISFET sensing array, operating in weak-inversion and consuming 6 \si{\micro\watt}. Using this application-specific integrated circuit (ASIC), the first ISFET array powered by body heat is demonstrated and the feasibility of using near-field communication (NFC) for wireless powering and data transfer is shown. The thesis also presents circuits and systems for combatting three key non-ideal effects experienced by CMOS ISFETs, namely temperature variation, threshold voltage offset and drift. An improvement in temperature sensitivity by a factor of three compared to an uncompensated design is shown through measured results, while adding less than 70 \si{\nano\watt} to the design. A method of automatically biasing the sensors is presented and an approach to using spatial separation of sensors in arrays in applications with flowing fluids is proposed for distinguishing between signal and sensor drift. A wearable device using the ISFET-based system is designed and tested with both artificial and natural sweat, identifying the remaining challenges that exist with both the sensors themselves and accompanying components such as microfluidics and reference electrode. A new ASIC is designed based on the discoveries of this work and aimed at detecting multiple analytes on a single chip. %Removed In the latter half of the thesis, Finally, the future directions of wearable electrochemical sensors is discussed with a look towards embedded machine learning to aid the interpretation of complex fluid with time-domain sensor arrays. The contributions of this thesis aim to form a foundation for the use of ISFETs in wearable devices to enable non-invasive physiological monitoring.Open Acces

CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications

Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non- Linear (ELIN) systems. They can handle large-signals in a low power environment under half the capacitor area required by the more popular ELIN Log-domain filters. Their inherent class-AB nature stems from the odd property of the sinh function at the heart of their companding operation. Despite this early realisation, the Sinh filtering paradigm has not attracted the interest it deserves to date probably due to its mathematical and circuit-level complexity. This Thesis presents an overview of the CMOS weak inversion Sinh filtering paradigm and explains how biomedical systems of low- to audio-frequency range could benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of high order Sinh continuous–time filters and more importantly to confirm their micro-power consumption and 100+ dB of DR through measured results presented for the first time. Novel high order Sinh topologies are designed by means of a systematic mathematical framework introduced. They employ a recently proposed CMOS Sinh integrator comprising only p-type devices in its translinear loops. The performance of the high order topologies is evaluated both solely and in comparison with their Log domain counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a corresponding and also novel Log domain class-AB topology, confirming that Sinh filters constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense of higher complexity and power consumption. The theoretical findings are validated by means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a 0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of ~60dB and 74μW power consumption from 2V power supply

Optimized Biosignals Processing Algorithms for New Designs of Human Machine Interfaces on Parallel Ultra-Low Power Architectures

The aim of this dissertation is to explore Human Machine Interfaces (HMIs) in a variety of biomedical scenarios. The research addresses typical challenges in wearable and implantable devices for diagnostic, monitoring, and prosthetic purposes, suggesting a methodology for tailoring such applications to cutting edge embedded architectures. The main challenge is the enhancement of high-level applications, also introducing Machine Learning (ML) algorithms, using parallel programming and specialized hardware to improve the performance. The majority of these algorithms are computationally intensive, posing significant challenges for the deployment on embedded devices, which have several limitations in term of memory size, maximum operative frequency, and battery duration. The proposed solutions take advantage of a Parallel Ultra-Low Power (PULP) architecture, enhancing the elaboration on specific target architectures, heavily optimizing the execution, exploiting software and hardware resources. The thesis starts by describing a methodology that can be considered a guideline to efficiently implement algorithms on embedded architectures. This is followed by several case studies in the biomedical field, starting with the analysis of a Hand Gesture Recognition, based on the Hyperdimensional Computing algorithm, which allows performing a fast on-chip re-training, and a comparison with the state-of-the-art Support Vector Machine (SVM); then a Brain Machine Interface (BCI) to detect the respond of the brain to a visual stimulus follows in the manuscript. Furthermore, a seizure detection application is also presented, exploring different solutions for the dimensionality reduction of the input signals. The last part is dedicated to an exploration of typical modules for the development of optimized ECG-based applications

Embedded computing systems design: architectural and application perspectives

Questo elaborato affronta varie problematiche legate alla progettazione e all'implementazione dei moderni sistemi embedded di computing, ponendo in rilevo, e talvolta in contrapposizione, le sfide che emergono all'avanzare della tecnologia ed i requisiti che invece emergono a livello applicativo, derivanti dalle necessità degli utenti finali e dai trend di mercato. La discussione sarà articolata tenendo conto di due punti di vista: la progettazione hardware e la loro applicazione a livello di sistema. A livello hardware saranno affrontati nel dettaglio i problemi di interconnettività on-chip. Aspetto che riguarda la parallelizzazione del calcolo, ma anche l'integrazione di funzionalità eterogenee. Sarà quindi discussa un'architettura d'interconnessione denominata Network-on-Chip (NoC). La soluzione proposta è in grado di supportare funzionalità avanzate di networking direttamente in hardware, consentendo tuttavia di raggiungere sempre un compromesso ottimale tra prestazioni in termini di traffico e requisiti di implementazioni a seconda dell'applicazione specifica. Nella discussione di questa tematica, verrà posto l'accento sul problema della configurabilità dei blocchi che compongono una NoC. Quello della configurabilità, è un problema sempre più sentito nella progettazione dei sistemi complessi, nei quali si cerca di sviluppare delle funzionalità, anche molto evolute, ma che siano semplicemente riutilizzabili. A tale scopo sarà introdotta una nuova metodologia, denominata Metacoding che consiste nell'astrarre i problemi di configurabilità attraverso linguaggi di programmazione di alto livello. Sulla base del metacoding verrà anche proposto un flusso di design automatico in grado di semplificare la progettazione e la configurazione di una NoC da parte del designer di rete. Come anticipato, la discussione si sposterà poi a livello di sistema, per affrontare la progettazione di tali sistemi dal punto di vista applicativo, focalizzando l'attenzione in particolare sulle applicazioni di monitoraggio remoto. A tal riguardo saranno studiati nel dettaglio tutti gli aspetti che riguardano la progettazione di un sistema per il monitoraggio di pazienti affetti da scompenso cardiaco cronico. Si partirà dalla definizione dei requisiti, che, come spesso accade a questo livello, derivano principalmente dai bisogni dell'utente finale, nel nostro caso medici e pazienti. Verranno discusse le problematiche di acquisizione, elaborazione e gestione delle misure. Il sistema proposto introduce vari aspetti innovativi tra i quali il concetto di protocollo operativo e l'elevata interoperabilità offerta. In ultima analisi, verranno riportati i risultati relativi alla sperimentazione del sistema implementato. Infine, il tema del monitoraggio remoto sarà concluso con lo studio delle reti di distribuzione elettrica intelligenti: le Smart Grid, cercando di fare uno studio dello stato dell'arte del settore, proponendo un'architettura di Home Area Network (HAN) e suggerendone una possibile implementazione attraverso Commercial Off the Shelf (COTS)