A 5 GHz Direct Digital Synthesizer MMIC with Direct Modulation and Spur Randomization

Abstract-This paper presents a low power, ultra high speed and high resolution SiGe DDS MMIC with 24-bit phase and 10-bit amplitude resolution. The DDS MMIC has the capabilities of direct frequency and phase modulations with 24 bit and 12 bit resolution, respectively. It is the first reported mm-wave DDS with direct digital frequency and phase modulation capabilities. Utilizing a 13-bit built-in ultra high speed pseudorandom binary sequence (PRBS) generator, the DDS MMIC can perform least significant bit (LSB) dithering for spur randomization. With more than twenty thousand transistors, the DDS MMIC includes a 24-bit ripple carry accumulator for phase accumulation, a 12-bit ripple carry adder for phase modulation, an LSB dithering block for spur randomization and a 10-bit segmented sine-weighted DAC for phase to amplitude mapping and digital to analog conversion. The DDS core occupies 3.0×2.5 mm 2 and consumes 4.7 W power under a single 3.3 V power supply. The Nyquist band SFDR is measured as 38 dBc with 469.360351 MHz output under 5.0 GHz maximum clock (FCW = 0x180800). With 1.246258914 GHz output frequency (FCW = 0x3FCFE7), the narrow band SFDR is measured as 82 dBc. The DDS MMIC is packaged and tested in LCC-68 cavity. Index Terms-digital-to-analog converter (DAC), direct digital synthesizer (DDS), direct digital frequency synthesizer (DDFS), sine-weighted digital-to-analog converter, Rom-less DDS, frequency modulation (FM), phase modulation (PM

Review of high-speed phase accumulator for direct digital frequency synthesizer

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed

Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA)

Direct digital synthesis is a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such a high-speed switching, fine- tuning and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate the signal integrity issues associated with the DDS design. In order to minimize the size of the lookup table to save hardware and lower the power consumption, we normally truncate the phase word output from the phase accumulator in the standard approach of designing DDS. However, this process will generate spurious frequencies (spurs), which degrade the quality of the output signals. It is considered one of the main signal integrity issues in the DDS design. Previous research introduces a novel spurs-free truncation method for compressing the lookup table to avoid using phase truncation without significant hardware change. This thesis aims to implement this DDS with novel truncation spurs-free structure and test it in a practical environment. It does so by providing a tutorial on designing, implementing and simulating the DDS on an Altera DE2-115 FPGA using Altera Quartus II FPGA design software and ModelSim Simulator. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with novel truncation spurs-free structure. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality

Síntese Digital Direta

Os projetos tradicionais de sintetizadores de frequência de elevada largura de banda utilizam um circuito fechado de fase (PLL). Um sintetizador digital direto, ou na terminologia inglesa, Direct Digital Dynthesis (DDS) oferece muitas vantagens significativas sobre as abordagens PLL como, por exemplo, um tempo de estabilização rápido, resolução de frequência sub-Hertz, resposta de comutação de fase contínua e baixo ruído de fase. Embora o princípio do DDS seja conhecido há muitos anos, o DDS não desempenhou um papel dominante na geração de frequência de banda larga até recentemente. Os DDSs iniciais eram limitados a produzir frequências estreitamente espaçadas com pequena largura de banda, devido a limitações da lógica digital e das tecnologias de conversão D/A. As vantagens recentes nas tecnologias de circuitos integrados (CI) trouxeram um progresso notável nesta área. Ao programar um DDS, é possível adaptar as larguras de banda de canal, formatos de modulação, salto de frequência e taxas de dados. Este é um passo importante em direção a um “software-rádio” que pode ser usado em vários sistemas. Um DDS pode ser aplicado no modulador ou demodulador nos sistemas de comunicação. O objetivo desta pesquisa foi encontrar um frontend ideal para um transmissor, concentrando-se nas implementações de circuito do DDS, mas a pesquisa também inclui a interface para circuitos de banda base e aspetos de design de nível de sistema de sistemas de comunicação digital.Traditional high-bandwidth frequency synthesizer designs utilize a phase closed loop (PLL). A direct digital synthesizer, or in English terminology, Direct Digital Dynthesis (DDS) offers many significant advantages over PLL approaches such as a fast-settling time, sub-Hertz frequency resolution, continuous phase switching response and low phase noise. Although the principle of DDS has been known for many years, DDS has not played a dominant role in broadband frequency generation until recently. Early DDSs were limited to producing closely spaced frequencies with low bandwidth, due to limitations of digital logic and D/A conversion technologies. Recent advances in integrated circuit (IC) technologies have brought remarkable progress in this area. When programming a DDS, it is possible to adapt channel bandwidths, modulation formats, frequency hopping and data rates. This is an important step towards “radio software” that can be used on multiple systems. A DDS can be applied in the modulator or demodulator in the communication systems. The purpose of this research was to find an ideal frontend for a transmitter, focusing on the circuit implementations of DDS, but the research also includes the interface to baseband circuits and system-level design aspects of digital communication systems

Ultra Low-Power Frequency Synthesizers for Duty Cycled IoT radios

Internet of Things (IoT), which is one of the main talking points in the electronics industry today, consists of a number of highly miniaturized sensors and actuators which sense the physical environment around us and communicate that information to a central information hub for further processing. This agglomeration of miniaturized sensors helps the system to be deployed in previously impossible arenas such as healthcare (Body Area Networks - BAN), industrial automation, real-time monitoring environmental parameters and so on; thereby greatly improving the quality of life. Since the IoT devices are usually untethered, their energy sources are limited (typically battery powered or energy scavenging) and hence have to consume very low power. Today's IoT systems employ radios that use communication protocols like Bluetooth Smart; which means that they communicate at data rates of a few hundred kb/s to a few Mb/s while consuming around a few mW of power. Even though the power dissipation of these radios have been decreasing steadily over the years, they seem to have reached a lower limit in the recent times. Hence, there is a need to explore other avenues to further reduce this dissipation so as to further improve the energy autonomy of the IoT node. Duty cycling has emerged as a promising alternative in this sense since it involves radios transmitting very short bursts of data at high rates and being asleep the rest of the time. In addition, high data rates proffer the added advantage of reducing network congestion which has become a major problem in IoT owing to the increase in the number of sensor nodes as well as the volume of data they send. But, as the average power (energy) dissipated decreases due to duty cycling, the energy overhead associated with the start-up phase of the radio becomes comparable with the former. Therefore, in order to take full advantage of duty cycling, the radio should be capable of being turned ON/OFF almost instantaneously. Furthermore, the radio of the future should also be able to support easy frequency hopping to improve the system efficiency from an interference point of view. In other words, in addition to high data rate capability, the next generation radios must also be highly agile and have a low energy overhead. All these factors viz. data rate, agility and overhead are mainly dependent on the radio's frequency synthesizer and therefore emphasis needs to be laid on developing new synthesizer architectures which are also amenable to technology scaling. This thesis deals with the evolution of one such all-digital frequency synthesizer; with each step dealing with one of the aforementioned issues. In order to reduce the energy overhead of the synthesizer, FBAR resonators (which are a class of MEMS resonators) are used as the frequency reference instead of a traditional quartz crystal. The FBAR resonators aid the design of fast-startup oscillators as opposed to the long latency associated with the start-up of the crystal oscillator. In addition, the frequency stability of the FBAR lends itself to open-loop architecture which can support very high data rates. Another advantage of the open-loop architecture is the frequency agility which aids easy channel switching for multi-hop architectures, as demonstrated in this thesis

Proceedings of the Second International Mobile Satellite Conference (IMSC 1990)

Presented here are the proceedings of the Second International Mobile Satellite Conference (IMSC), held June 17-20, 1990 in Ottawa, Canada. Topics covered include future mobile satellite communications concepts, aeronautical applications, modulation and coding, propagation and experimental systems, mobile terminal equipment, network architecture and control, regulatory and policy considerations, vehicle antennas, and speech compression

Proceedings of the Third International Mobile Satellite Conference (IMSC 1993)

Satellite-based mobile communications systems provide voice and data communications to users over a vast geographic area. The users may communicate via mobile or hand-held terminals, which may also provide access to terrestrial cellular communications services. While the first and second International Mobile Satellite Conferences (IMSC) mostly concentrated on technical advances, this Third IMSC also focuses on the increasing worldwide commercial activities in Mobile Satellite Services. Because of the large service areas provided by such systems, it is important to consider political and regulatory issues in addition to technical and user requirements issues. Topics covered include: the direct broadcast of audio programming from satellites; spacecraft technology; regulatory and policy considerations; advanced system concepts and analysis; propagation; and user requirements and applications

Muon (g-2) Technical Design Report

The Muon (g-2) Experiment, E989 at Fermilab, will measure the muon anomalous magnetic moment a factor-of-four more precisely than was done in E821 at the Brookhaven National Laboratory AGS. The E821 result appears to be greater than the Standard-Model prediction by more than three standard deviations. When combined with expected improvement in the Standard-Model hadronic contributions, E989 should be able to determine definitively whether or not the E821 result is evidence for physics beyond the Standard Model. After a review of the physics motivation and the basic technique, which will use the muon storage ring built at BNL and now relocated to Fermilab, the design of the new experiment is presented. This document was created in partial fulfillment of the requirements necessary to obtain DOE CD-2/3 approval

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities