2,121 research outputs found
μνλλ¬Όμ λμ κ²½ μκ·Ήμ μν μμ μ΄μν μ κ²½μκ·ΉκΈ°
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Όλ¬Έ(λ°μ¬)--μμΈλνκ΅ λνμ :곡과λν μ κΈ°Β·μ 보곡νλΆ,2020. 2. κΉμ±μ€.In this study, a fully implantable neural stimulator that is designed to stimulate the brain in the small animal is described. Electrical stimulation of the small animal is applicable to pre-clinical study, and behavior study for neuroscience research, etc. Especially, behavior study of the freely moving animal is useful to observe the modulation of sensory and motor functions by the stimulation. It involves conditioning animal's movement response through directional neural stimulation on the region of interest. The main technique that enables such applications is the development of an implantable neural stimulator. Implantable neural stimulator is used to modulate the behavior of the animal, while it ensures the free movement of the animals. Therefore, stable operation in vivo and device size are important issues in the design of implantable neural stimulators. Conventional neural stimulators for brain stimulation of small animal are comprised of electrodes implanted in the brain and a pulse generation circuit mounted on the back of the animal. The electrical stimulation generated from the circuit is conveyed to the target region by the electrodes wire-connected with the circuit. The devices are powered by a large battery, and controlled by a microcontroller unit. While it represents a simple approach, it is subject to various potential risks including short operation time, infection at the wound, mechanical failure of the device, and animals being hindered to move naturally, etc. A neural stimulator that is miniaturized, fully implantable, low-powered, and capable of wireless communication is required.
In this dissertation, a fully implantable stimulator with remote controllability, compact size, and minimal power consumption is suggested for freely moving animal application. The stimulator consists of modular units of surface-type and depth-type arrays for accessing target brain area, package for accommodating the stimulating electronics all of which are assembled after independent fabrication and implantation using customized flat cables and connectors. The electronics in the package contains ZigBee telemetry for low-power wireless communication, inductive link for recharging lithium battery, and an ASIC that generates biphasic pulse for neural stimulation. A dual-mode power-saving scheme with a duty cycling was applied to minimize the power consumption. All modules were packaged using liquid crystal polymer (LCP) to avoid any chemical reaction after implantation.
To evaluate the fabricated stimulator, wireless operation test was conducted. Signal-to-Noise Ratio (SNR) of the ZigBee telemetry were measured, and its communication range and data streaming capacity were tested. The amount of power delivered during the charging session depending on the coil distance was measured. After the evaluation of the device functionality, the stimulator was implanted into rats to train the animals to turn to the left (or right) following a directional cue applied to the barrel cortex. Functionality of the device was also demonstrated in a three-dimensional maze structure, by guiding the rats to navigate better in the maze. Finally, several aspects of the fabricated device were discussed further.λ³Έ μ°κ΅¬μμλ μν λλ¬Όμ λλλ₯Ό μκ·ΉνκΈ° μν μμ μ΄μν μ κ²½μκ·ΉκΈ°κ° κ°λ°λμλ€. μν λλ¬Όμ μ κΈ°μκ·Ήμ μ μμ μ°κ΅¬, μ κ²½κ³Όν μ°κ΅¬λ₯Ό μν νλμ°κ΅¬ λ±μ νμ©λλ€. νΉν, μμ λ‘κ² μμ§μ΄λ λλ¬Όμ λμμΌλ‘ ν νλ μ°κ΅¬λ μκ·Ήμ μν κ°κ° λ° μ΄λ κΈ°λ₯μ μ‘°μ μ κ΄μ°°νλ λ° μ μ©νκ² νμ©λλ€. νλ μ°κ΅¬λ λλμ νΉμ κ΄μ¬ μμμ μ§μ μ μΌλ‘ μκ·Ήνμ¬ λλ¬Όμ νλλ°μμ 쑰건ννλ λ°©μμΌλ‘ μνλλ€. μ΄λ¬ν μ μ©μ κ°λ₯μΌ νλ ν΅μ¬κΈ°μ μ μ΄μν μ κ²½μκ·ΉκΈ°μ κ°λ°μ΄λ€. μ΄μν μ κ²½μκ·ΉκΈ°λ λλ¬Όμ μμ§μμ λ°©ν΄νμ§ μμΌλ©΄μλ κ·Έ νλμ μ‘°μ νκΈ° μν΄ μ¬μ©λλ€. λ°λΌμ λλ¬Ό λ΄μμμ μμ μ μΈ λμκ³Ό μ₯μΉμ ν¬κΈ°κ° μ΄μν μ κ²½μκ·ΉκΈ°λ₯Ό μ€κ³ν¨μ μμ΄ μ€μν λ¬Έμ μ΄λ€. κΈ°μ‘΄μ μ κ²½μκ·ΉκΈ°λ λλμ μ΄μλλ μ κ·Ή λΆλΆκ³Ό, λλ¬Όμ λ± λΆλΆμ μμΉν νλ‘λΆλΆμΌλ‘ ꡬμ±λλ€. νλ‘μμ μμ°λ μ κΈ°μκ·Ήμ νλ‘μ μ μ μΌλ‘ μ°κ²°λ μ κ·Ήμ ν΅ν΄ λͺ©ν μ§μ μΌλ‘ μ λ¬λλ€. μ₯μΉλ λ°°ν°λ¦¬μ μν΄ κ΅¬λλλ©°, λ΄μ₯λ λ§μ΄ν¬λ‘ 컨νΈλ‘€λ¬μ μν΄ μ μ΄λλ€. μ΄λ μ½κ³ κ°λ¨ν μ κ·Όλ°©μμ΄μ§λ§, 짧μ λμμκ°, μ΄μλΆμμ κ°μΌμ΄λ μ₯μΉμ κΈ°κ³μ κ²°ν¨, κ·Έλ¦¬κ³ λλ¬Όμ μμ°μ€λ¬μ΄ μμ§μ λ°©ν΄ λ± μ¬λ¬ λ¬Έμ μ μ μΌκΈ°ν μ μλ€. μ΄λ¬ν λ¬Έμ μ κ°μ μ μν΄ λ¬΄μ ν΅μ μ΄ κ°λ₯νκ³ , μ μ λ ₯, μννλ μμ μ΄μν μ κ²½μκ·ΉκΈ°μ μ€κ³κ° νμνλ€.
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Όμλμλ€.Chapter 1 : Introduction 1
1.1. Neural Interface 2
1.1.1. Concept 2
1.1.2. Major Approaches 3
1.2. Neural Stimulator for Animal Brain Stimulation 5
1.2.1. Concept 5
1.2.2. Neural Stimulator for Freely Moving Small Animal 7
1.3. Suggested Approaches 8
1.3.1. Wireless Communication 8
1.3.2. Power Management 9
1.3.2.1. Wireless Power Transmission 10
1.3.2.2. Energy Harvesting 11
1.3.3. Full implantation 14
1.3.3.1. Polymer Packaging 14
1.3.3.2. Modular Configuration 16
1.4. Objectives of This Dissertation 16
Chapter 2 : Methods 18
2.1. Overview 19
2.1.1. Circuit Description 20
2.1.1.1. Pulse Generator ASIC 21
2.1.1.2. ZigBee Transceiver 23
2.1.1.3. Inductive Link 24
2.1.1.4. Energy Harvester 25
2.1.1.5. Surrounding Circuitries 26
2.1.2. Software Description 27
2.2. Antenna Design 29
2.2.1. RF Antenna 30
2.2.1.1. Design of Monopole Antenna 31
2.2.1.2. FEM Simulation 31
2.2.2. Inductive Link 36
2.2.2.1. Design of Coil Antenna 36
2.2.2.2. FEM Simulation 38
2.3. Device Fabrication 41
2.3.1. Circuit Assembly 41
2.3.2. Packaging 42
2.3.3. Electrode, Feedthrough, Cable, and Connector 43
2.4. Evaluations 45
2.4.1. Wireless Operation Test 46
2.4.1.1. Signal-to-Noise Ratio (SNR) Measurement 46
2.4.1.2. Communication Range Test 47
2.4.1.3. Device Operation Monitoring Test 48
2.4.2. Wireless Power Transmission 49
2.4.3. Electrochemical Measurements In Vitro 50
2.4.4. Animal Testing In Vivo 52
Chapter 3 : Results 57
3.1. Fabricated System 58
3.2. Wireless Operation Test 59
3.2.1. Signal-to-Noise Ratio Measurement 59
3.2.2. Communication Range Test 61
3.2.3. Device Operation Monitoring Test 62
3.3. Wireless Power Transmission 64
3.4. Electrochemical Measurements In Vitro 65
3.5. Animal Testing In Vivo 67
Chapter 4 : Discussion 73
4.1. Comparison with Conventional Devices 74
4.2. Safety of Device Operation 76
4.2.1. Safe Electrical Stimulation 76
4.2.2. Safe Wireless Power Transmission 80
4.3. Potential Applications 84
4.4. Opportunities for Further Improvements 86
4.4.1. Weight and Size 86
4.4.2. Long-Term Reliability 93
Chapter 5 : Conclusion 96
Reference 98
Appendix - Liquid Crystal Polymer (LCP) -Based Spinal Cord Stimulator 107
κ΅λ¬Έ μ΄λ‘ 138
κ°μ¬μ κΈ 140Docto
Design and Development of Smart Brain-Machine-Brain Interface (SBMIBI) for Deep Brain Stimulation and Other Biomedical Applications
Machine collaboration with the biological body/brain by sending electrical information back and forth is one of the leading research areas in neuro-engineering during the twenty-first century. Hence, Brain-Machine-Brain Interface (BMBI) is a powerful tool for achieving such machine-brain/body collaboration. BMBI generally is a smart device (usually invasive) that can record, store, and analyze neural activities, and generate corresponding responses in the form of electrical pulses to stimulate specific brain regions. The Smart Brain-Machine-Brain-Interface (SBMBI) is a step forward with compared to the traditional BMBI by including smart functions, such as in-electrode local computing capabilities, and availability of cloud connectivity in the system to take the advantage of powerful cloud computation in decision making.
In this dissertation work, we designed and developed an innovative form of Smart Brain-Machine-Brain Interface (SBMBI) and studied its feasibility in different biomedical applications. With respect to power management, the SBMBI is a semi-passive platform. The communication module is fully passiveβpowered by RF harvested energy; whereas, the signal processing core is battery-assisted. The efficiency of the implemented RF energy harvester was measured to be 0.005%.
One of potential applications of SBMBI is to configure a Smart Deep-Brain-Stimulator (SDBS) based on the general SBMBI platform. The SDBS consists of brain-implantable smart electrodes and a wireless-connected external controller. The SDBS electrodes operate as completely autonomous electronic implants that are capable of sensing and recording neural activities in real time, performing local processing, and generating arbitrary waveforms for neuro-stimulation. A bidirectional, secure, fully-passive wireless communication backbone was designed and integrated into this smart electrode to maintain contact between the smart electrodes and the controller. The standard EPC-Global protocol has been modified and adopted as the communication protocol in this design. The proposed SDBS, by using a SBMBI platform, was demonstrated and tested through a hardware prototype. Additionally the SBMBI was employed to develop a low-power wireless ECG data acquisition device. This device captures cardiac pulses through a non-invasive magnetic resonance electrode, processes the signal and sends it to the backend computer through the SBMBI interface. Analysis was performed to verify the integrity of received ECG data
Low power digital baseband core for wireless Micro-Neural-Interface using CMOS sub/near-threshold circuit
This thesis presents the work on designing and implementing a low power digital baseband core with custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) System-on-Chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of distributed sensors, is designed to control the operation of individual MNI and communicate and control MNI devices implanted across the brain using received downlink commands from external base station and store/dump targeted neural data uplink in an energy efficient manner. The application specific protocol defines three modes (Time Stamp Mode, Streaming Mode and Snippet Mode) to extract neural signals with on-chip signal conditioning and discrimination. In Time Stamp Mode, Streaming Mode and Snippet Mode, the core executes basic on-chip spike discrimination and compression, real-time monitoring and segment capturing of neural signals so single spike timing as well as inter-spike timing can be retrieved with high temporal and spatial resolution. To implement the core control logic using sub/near-threshold logic, a novel digital design methodology is proposed which considers INWE (Inverse-Narrow-Width-Effect), RSCE (Reverse-Short-Channel-Effect) and variation comprehensively to size the transistor width and length accordingly to achieve close-to-optimum digital circuits. Ultra-low-power cell library containing 67 cells including physical cells and decoupling capacitor cells using the optimum fingers is designed, laid-out, characterized, and abstracted. A robust on-chip sense-amp-less SRAM memory (8X32 size) for storing neural data is implemented using 8T topology and LVT fingers. The design is validated with silicon tapeout and measurement shows the digital baseband core works at 400mV and 1.28 MHz system clock with an average power consumption of 2.2 ΞΌW, resulting in highest reported communication power efficiency of 290Kbps/ΞΌW to date
Low Power Circuit Design in Sustainable Self Powered Systems for IoT Applications
The Internet-of-Things (IoT) network is being vigorously pushed forward from many fronts in
diverse research communities. Many problems are still there to be solved, and challenges are found
among its many levels of abstraction. In this thesis we give an overview of recent developments
in circuit design for ultra-low power transceivers and energy harvesting management units for the
IoT.
The first part of the dissertation conducts a study of energy harvesting interfaces and optimizing
power extraction, followed by power management for energy storage and supply regulation. we
give an overview of the recent developments in circuit design for ultra-low power management
units, focusing mainly in the architectures and techniques required for energy harvesting from
multiple heterogeneous sources. Three projects are presented in this area to reach a solution that
provides reliable continuous operation for IoT sensor nodes in the presence of one or more natural
energy sources to harvest from.
The second part focuses on wireless transmission, To reduce the power consumption and boost
the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator
employed as the local oscillator generator scheme. In combination with an edge-combiner power
amplifier, the Tx showed a measured energy efficiency of 0.2 nJ=bit and a normalized energy
efficiency of 3.1 nJ=bit:mW when operating at output power levels up to -10 dBm and data rates
of 3 Mbps
Polymorphic computing abstraction for heterogeneous architectures
Integration of multiple computing paradigms onto system on chip (SoC) has pushed the boundaries of design space exploration for hardware architectures and computing system software stack. The heterogeneity of computing styles in SoC has created a new class of architectures referred to as Heterogeneous Architectures. Novel applications developed to exploit the different computing styles are user centric for embedded SoC. Software and hardware designers are faced with several challenges to harness the full potential of heterogeneous architectures. Applications have to execute on more than one compute style to increase overall SoC resource utilization. The implication of such an abstraction is that application threads need to be polymorphic. Operating system layer is thus faced with the problem of scheduling polymorphic threads. Resource allocation is also an important problem to be dealt by the OS. Morphism evolution of application threads is constrained by the availability of heterogeneous computing resources. Traditional design optimization goals such as computational power and lower energy per computation are inadequate to satisfy user centric application resource needs. Resource allocation decisions at application layer need to permeate to the architectural layer to avoid conflicting demands which may affect energy-delay characteristics of application threads. We propose Polymorphic computing abstraction as a unified computing model for heterogeneous architectures to address the above issues. Simulation environment for polymorphic applications is developed and evaluated under various scheduling strategies to determine the effectiveness of polymorphism abstraction on resource allocation. User satisfaction model is also developed to complement polymorphism and used for optimization of resource utilization at application and network layer of embedded systems
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