The integration of on-line monitoring and reconfiguration functions using IEEE1149.4 into a safety critical automotive electronic control unit.

This paper presents an innovative application of IEEE 1149.4 and the integrated diagnostic reconfiguration (IDR) as tools for the implementation of an embedded test solution for an automotive electronic control unit, implemented as a fully integrated mixed signal system. The paper describes how the test architecture can be used for fault avoidance with results from a hardware prototype presented. The paper concludes that fault avoidance can be integrated into mixed signal electronic systems to handle key failure modes

Dependable reconfigurable multi-sensor poles for security

Wireless sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical [1]. An example of a multi-sensor pole is shown. Crucial attribute in these systems for security, especially in harsh environment, is a high robustness and guaranteed availability during lifetime. This environment could include molest. In this paper, two approaches are used which are applied simultaneously but are developed in different projects. \u

Test Strategies for Embedded ADC Cores in a System-on-Chip, A Case Study

Testing of a deeply embedded mixed-signal core in a System-on-Chip (SoC) is a challenging issue due to the communication bottleneck in accessing the core from external automatic test equipment. Consequently, in many cases the preferred approach is built-in self-test (BIST), where the major part of test activity is performed within the unit-under-test and only final results are communicated to the external tester. IEEE Standard 1500 provides efficient test infrastructure for testing digital cores; however, its applications in mixed-signal core test remain an open issue. In this paper we address the problem of implementing BIST of a mixed-signal core in a IEEE Std 1500 test wrapper and discuss advantages and drawbacks of different test strategies. While the case study is focused on histogram based test of ADC, test strategies of other types of mixed-signal cores related to trade-off between performance (i.e., test time) and required resources are likely to follow similar conclusions

Integrity checking of 1149.4 extensions to 1149.1

The IEEE 1149.4 Standard for a Mixed-Signal (MS) Test Bus proposes an extension to the well-accepted IEEE 1149.1 boundary-scan test architecture, with the objective of facilitating interconnect, parametric and internal testing of MS circuits. An Analog Test Access Port (ATAP) comprising two pins called AT1 and AT2, and an internal analog bus (AB) comprising two lines (AB1, AB2), enable analog test stimulae and responses to be routed to any pin possessing an Analog Boundary Module (ABMs replace the IEEE 1149.1 test cells in the case of analog pins). A Test Bus Interface Circuit (TBIC) comprising ten analog switches defines how the ATAP and the internal analog bus are (dis)connected, and the six analog switches in each ABM define what connections should be established between the pin, the core circuitry, and the internal analog bus. The large number of analog switches in the 1149.4 test architecture may raise concerns about their integrity, particularly when they are used frequently, as would be the case in an 1149.4-based MS debug strategy. This paper proposes a set of integrity check procedures that address only the 1149.4 extensions: ATAP, TBIC, AB lines, ABMs

A built-in debugger for 1149.4 circuits

Debugging mixed-signal circuits is usually seen as a complex task due to the presence of an analog part and the necessary interaction with a digital part. The use of debug and test tools that require physical access suffers from the same restrictions that led to other solutions based on electronic access, especially for digital circuits, due to the increasing operating frequencies and miniaturization scales. This is particularly the case that led to the emergence and wide acceptance of the IEEE1149 family of test infrastructures, which relies on an electronic test access port. While the IEEE1149.4 test infrastructure enables the structural and parametric test of mixed-signal boards, its use is still far from reaching a wide acceptance, namely due to the lack of alternative applications, such as debugging, as it is the case in the 1149.1 domain. This work describes a way to support debug operations in 1149.4 mixed-signal circuits, in particular a built-in condition detection mechanism able to support internal watchpoint/breakpoint operations

Debugging mixed-signals circuits via the IEEE1149.4 - a built-in mixed condition detector

Diagnosing design faults in a mixed-signals circuit is no trivial task, due to the inherent uncertainties associated with analog signals, not mentioning the interaction between the analog part and the digital part. Using debug and test tools is one way to deal with the problem, especially during the prototyping phase, however if a physical access is required then the same restrictions that led to other solutions, based on electronic access, apply. This is particularly the case that led to the emergence and wide acceptance of the IEEE1149 family of test infrastructures, which relies on an electronic test access port. While the IEEE1149.4 test infrastructure enables the structural and parametric test of mixed-signal boards, its use is still far from reaching a wide acceptance, namely due to the lack of alternative applications, such as debugging, as it is the case in the 1149.1 domain of purely digital circuits. Building upon the rationale that enabled transferring the structural test of board interconnections between analog pins, from the analog domain to the digital domain, using the mechanisms present in an Analog Boundary Module, as defined in the IEEE1149.4 std., we propose a new way to support debug operations in 1149.4 mixed-signal circuits. In particular, we describe a built-in mechanism able to detect both internal and pin-level mixed-signal conditions, and hence able to support watchpoint/breakpoint operations at the IC level

Remote controlled experiments for teaching over the Internet: A comparison of approaches developed in the PEARL project

The PEARL project has been developing approaches for enabling real-world experiments to be conducted by students working, remotely from the laboratory, over the Internet. This paper describes these approaches and compares and contrasts three specific implementations of them both at the level of the nature of the practical work they support and the technical infrastructures that enables this to be conducted remotely. Initial evaluations by experts and representative student subjects are reported and key lessons for further development work by the project consortium, or others seeking to implement remote experiments, are outlined. Among the lessons learnt is that engineering realities associated with the equipment being used were difficult to accommodate in the generic architecture we initially envisaged. In fact the three implementations described adopted different architecture in their realisation of the PEARL approach. These are commented on in the paper together with notes on their implementation given available technologies