Techniques for low jitter clock multiplication

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 115-121).Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to path mismatch in the detector as well as analog nonidealities in the tuning circuits. This thesis proposes a mostly-digital tuning technique that drastically reduces deterministic jitter in phase realigning clock multipliers. The proposed technique eliminates path mismatch by using a single-path digital detection method that leverages a scrambling time-to-digital converter (TDC) and correlated double sampling to infer the tuning error from the difference in cycle periods of the output. By using a digital loop filter that consists of a digital accumulator, the tuning technique avoids the analog nonidealities of typical tuning paths. The scrambling TDC is not a contribution of this thesis. A highly-digital MDLL prototype that uses the proposed tuning technique consists of two custom 0.13 [mu]m ICs, an FPGA board, a discrete digital-to-analog converter (DAC) with effective 8 bits, and a simple RC filter. The measured performance (for a 1.6 GHz output and 50 MHz reference) demonstrated an overall jitter of 0.93 ps rms, and estimated random and deterministic jitter of 0.68 ps rms and 0.76 ps peak-to-peak, respectively. The proposed MDLL architecture is especially suitable for digital ICs, since its highly-digital architecture is mostly compatible with digital design flows, which eases its porting between technologies.by Belal Moheedin Helal.Ph.D

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.

Special Topics in Information Technology

This open access book presents outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the best theses defended in 2021-22 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

Special Topics in Information Technology

This open access book presents outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the best theses defended in 2021-22 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

CERN CAMAC News Issue #11 March 1977 Special Issue: CAMAC Product Guide

CAMAC is a means of interconnecting many peripheral devices through a digital data highway to a data processing device such as a computer

A comparison of the polarization observables for the d(e, e\u27p) and P(e, e\u27p) reactions at quasi-free kinematics

Final-state recoil proton polarization observables were measured using the newly commissioned Proton Focal-Plane-Polarimeter at the MIT-Bates Linear Accelerator Center. This device permits access to a new class of electromagnetic spin observables. Measurements were made at two values of {dollar}{lcub}\cal Q{rcub}\sp2,{dollar} 0.38 and 0.50 (GeV/c){dollar}\sp2,{dollar} in the quasi-elastic region using the {dollar}d(\vec e,e\sp\prime\vec p)n{dollar} reaction in parallel kinematics with zero recoil momentum. Simultaneous measurements were also made using the {dollar}p(\vec e,e\sp\prime\vec p){dollar} reaction at the same kinematics allowing a precise comparison between the hydrogen and deuterium spin-dependent observables, {dollar}D\sb{lcub}LL{rcub}{dollar} and {dollar}D\sb{lcub}LT{rcub}{dollar} as well as the induced polarization {dollar}P\sb{lcub}n{rcub}.{dollar} In the elastic scattering limit the spin observables can be used to directly extract the ratio of {dollar}G\sbsp{lcub}E{rcub}{lcub}p{rcub}/G\sbsp{lcub}M{rcub}{lcub}p{rcub}.{dollar} Therefore, in the impulse approximation the results have direct bearing on the validity of approximations used to extract {dollar}G\sbsp{lcub}E{rcub}{lcub}n{rcub}/G\sbsp{lcub}M{rcub}{lcub}n{rcub}{dollar} for the neutron in analogous {dollar}d(\vec e,e\sp\prime\vec n)p{dollar} experiments. This comparison is also nearly free of systematic errors and is independent of both the beam polarization and the analyzing power of the {dollar}\sp{lcub}12{rcub}C(p,p\sp\prime){dollar} reaction. The results for deuterium are in good agreement with the hydrogen data and with the Plane-Wave-Impulse-Approximation theories of Arenhovel and Van Orden

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed

Development of readout electronics for the ATLAS tile calorimeter at the HL-LHC

El Gran Colisionador de Hadrones (LHC) es uno de los experimentos más grandes en el mundo. El LHC ha sido diseñado para explorar las fronteras de la física, descubriendo el bosón de Higgs en el año 2012 a través de una colaboración compuesta por más de 7,000 científicos e ingenieros. Durante el año 2026 el acelerador LHC sufrirá una actualización que dará paso al nuevo acelerador High Luminosity LHC (HL-LHC). El nuevo acelerador aumentará la luminosidad instantánea en un factor 5 comparado con el actual LHC y hasta un factor 10 la lumninosidad integrada. El diseño del HL-LHC y la consecuente actualización de los experimentos instalados en él, representa un desafío tecnológico excepcional. Este nuevo acelerador conlleva el desarrollo de nuevas tecnologías de aceleradores como imanes superconductores y cavidades, así como sistemas electrónicos que permiten adquirir y procesar la extraordinaria cantidad de datos que se generarán. Esta tesis se desarrolla dentro del marco del proyecto Demonstrator. Este proyecto pretende la evaluación y cualificación del funcionamiento de la electrónica de adquisición para el HL-LHC antes de su instalación en el subdetector ATLAS Tile Calorimeter. El proyecto Demonstrator no sólo abarca programas de pruebas de la nueva electrónica con haces de partículas (testbeam), sino la instalación de un módulo Demonstrator dentro del detector ATLAS incluyendo nuevos desarrollos electrónicos llevados a cabo para el HL-LHC. El módulo Demonstrator ha sido probado en varias campañas de evaluación con haces de partículas. Este módulo consta de 4 estructuras mecánicas de aluminio (mini-drawers) donde cada una alberga 12 fotomultiplicadores, una tarjeta MainBoard y una tarjeta DaughterBoard cuya función es la de transmitir las señales digitalizadas de los PMTs al sistema de adquisición fuera del detector. En la parte más alejada del detector se encuentra el Tile PreProcessor (TilePPr), que es el primer y más importante componente del sistema de adquisición de datos del detector ATLAS Tile Calorimeter en el HL-LHC. Este prototipo integra dos FPGAs de alta generación para la procesado de datos recibidos del módulo "Demonstrator". Además, el TilePPr es responsable de la distribución del reloj en todo el detector, así como de transmitir los comandos de configuraci ón para seleccionar los diferentes modos de operación del módulo. La comunicación con el detector se realiza a través de cuatro módulos ópticos QSFP que proporcionan un ancho de banda de 160 Gbps. En esta tesis se presenta el diseño del primer prototipo TilePPr diseñado para la operación y lectura del módulo Demonstrator, así como los desarrollos firmware que se han realizado para la tarjeta DaughterBoard y TilePPr, en especial para los enlaces ópticos de alta velocidad. Además esta tarjeta se ha utilizado durante tres campañas de pruebas con haces de partículas donde se ha demonstrado su correcto funcionamiento como sistema de adquisición y como sistema para la distribución del reloj. Este documento se estructura en siete capítulos. El primer capítulo introduce el detector Tile Calorimeter y el sistema de selección de eventos actualmente utilizado en el ATLAS. Especialmente se centra en el principio de operación del detector, ya que no cambiará en el HL-LHC. El segundo capítulo introduce al HL-LHC así como a las actualizaciones necesarias en el experimento ATLAS para poder cumplir con los nuevos requerimientos. También se detalla los desarrollos electrónicos para el HL-LHC dentro del marco del proyecto Demonstrator, describiendo, por tanto, los detalles técnicos de los sistemas de electrónica de front-end y back-end. El tercer capítulo trata el diseño de la tarjeta TilePPr. Presenta los requerimientos y elementos fundamentales que la componen. Se incluyen también los detalles del proceso de diseño, desde la concepción de la tarjeta hasta los detalles físicos de la misma, acompañados de simulaciones de integridad de la señal y pruebas de verificación realizadas sobre el prototipo final. En el cuarto capítulo se abarca una descripción de los módulos firmware, tanto para el front-end como para el back-end, necesarios para la operación del módulo Demonstrator. En este capítulo se pone un énfasis especial en el desarrollo de los enlaces de alta velocidad, así como los aspectos que se han tenido en cuenta durante su diseño para que proporcionen una latencia fija y determinista. En un quinto capítulo se detalla el desarrollo de herramientas digitales implementadas en FPGA para la monitorización de diferencias de fase entre relojes. Este capítulo detalla las técnicas de undersampling utilizadas actualmente para la medida de diferencias de fases, y se propone un nuevo circuito basado en técnicas de undersampling que mejoran las capacidades del original. Además se muestran los resultados experimentales obtenidos y se explica las aplicaciones e implementación del circuito propuesto en el TilePPr para la sincronización del módulo con el reloj del LHC y monitorización de diferencias de fase. El capítulo sexto, introduce a las pruebas realizadas con haces de hadrones donde se puede ver el conjunto de la electrónica del front-end y back-end. Además se muestran análisis de los datos obtenidos que permite la comparación entre la electrónica actual y la diseñada para el HL-LHC. Finalmente se incluyen las conclusiones de esta tesis, así como el trabajo futuro vinculado a la continuación de la línea de investigación presentada.The Large Hadron Collider (LHC) is one of largest particle accelerators in the world. It has been used to explore energy frontier physics since 2010, with a collaboration composed of more than 7,000 scientists from 60 different countries. After a major upgrade that will occur in the 2020s, the LHC will become the High Luminosity LHC (HL-LHC). The HL-LHC will increase the instantaneous luminosity by a factor 5 compared to the LHC. The integrated luminosity of the HL-LHC program will be 10 times the integrated luminosity of LHC. The R&D HL-LHC efforts involve a large community in Europe, but also in the US and Japan. The design of the HL-LHC and the consequent upgrade of the experiments at the HL-LHC represents an exceptional technological challenge. New accelerator technologies are under development such as superconducting magnets and cavities and high-throughput electronics to receive and process the extraordinary amount of data generated by the experiments. In addition, the new readout and trigger architecture planned for the ATLAS in the HL-LHC requires a complete redesign of the front-end and back-end electronics systems to cope with the new requirements in radiation levels, data bandwidth and clocking distribution. This thesis is focused on the development of readout electronics for the ATLAS experiment at the HL-LHC, particularly in the design of the Tile Preprocessor (TilePPr) prototype envisaged for the readout of the Tile Calorimeter and communication with the ATLAS trigger system. Chapters 1 and 2 present an introduction to the LHC and HL-LHC experiments, followed by an extensive review of the Tile Calorimeter and the plans for the ATLAS Phase II Upgrade for the HL-LHC. The TilePPr prototype hardware design is fully described in Chapter 3, followed by the result of signal integrity simulations that confirmed the correct design of the PCB. At the end of the chapter some experimental results obtained during the initial tests with the first prototypes are presented. Chapter 4 describes all the firmware developments implemented for the operation of the Demonstrator module in the TilePPr prototype and in the DaughterBoard. This chapter includes a detailed description of all the firmware blocks designed for the front-end and back-end electronics, focusing in the development of high-speed data links with fixed and deterministic latency. Chapter 5 presents the development of FPGA-based circuits for the precise measurement of phase differences between clocks. A phase measurement circuit, called OSUS, based on oversampling techniques is discussed. The experimental results with the OSUS circuit obtained from its implementation in the TilePPr prototype are presented here. The OSUS circuit permits the synchronization of the Demonstrator module and the LHC clock, as well as the monitoring of the phase stability of clocks with a precision of about 30 psRMS. Chapter 6 includes a description of the testbeam setup and some experimental physics results obtained. During these testbeam campaigns the TilePPr prototype was the main readout system in the back-end electronics operating the Demonstrator module. Finally, the conclusions and future plans for this work are given at the end of this document

Design and Implementation of a Re-Configurable Arbitrary Signal Generator and Radio Frequency Spectrum Analyser

This research is focused on the design, simulation and implementation of a reconfigurable arbitrary signal generator and the design, simulation and implementation of a radio frequency spectrum analyser based on digital signal processing. Until recently, Application Specific Integrated Circuits (ASICs) were used to produce high performance re-configurable function and arbitrary waveform generators with comprehensive modulation capabilities. However, that situation is now changing with the availability of advanced but low cost Field Programmable Gate Arrays (FPGAs), which could be used as an alternative to ASICs in these applications. The availability of high performance FPGA families opens up the opportunity to compete with ASIC solutions at a fraction of the development cost of an ASIC solution. A fast digital signal processing algorithm for digital waveform generation, using primarily but not limited to Direct Digital Synthesis (DDS) technologies, developed and implemented in a field-configurable logic, with control provided by an embedded microprocessor replacing a high cost ASIC design appeared to be a very attractive concept. This research demonstrates that such a concept is feasible in its entirety. A fully functional, low-complexity, low cost, pulse, Gaussian white noise and DDS based function and arbitrary waveform generator, capable of being amplitude, frequency and phase modulated by an internally generated or external modulating signal was implemented in a low-cost FPGA. The FPGA also included the capabilities to perform pulse width modulation and pulse delay modulation on pulse waveforms. Algorithms to up-convert the sampling rate of the external modulating signal using Cascaded Integrator Comb (CIC) filters and using interpolation method were analysed. Both solutions were implemented to compare their hardware complexities. Analysis of generating noise with user-defined distribution is presented. The ability of triggering the generator by an internally generated or an external event to generate a burst of waveforms where the time between the trigger signal and waveform output is fixed was also implemented in the FPGA. Finally, design of interface to a microprocessor to provide control of the versatile waveform generator was also included in the FPGA. This thesis summarises the literature, design considerations, simulation and implementation of the generator design. The second part of the research is focused on radio frequency spectrum analysis based on digital signal processing. Most existing spectrum analysers are analogue in nature and their complexity increases with frequency. Therefore, the possibility of using digital techniques for spectrum analysis was considered. The aim was to come up with digital system architecture for spectrum analysis and to develop and implement the new approach on a suitable digital platform. This thesis analyses the current literature on shifting algorithms to remove spurious responses and highlights its drawbacks. This thesis also analyses existing literature on quadrature receivers and presents novel adaptation of the existing architectures for application in spectrum analysis. A wide band spectrum analyser receiver with compensation for gain and phase imbalances in the Radio Frequency (RF) input range, as well as compensation for gain and phase imbalances within the Intermediate Frequency (IF) pass band complete with Resolution Band Width (RBW) filtering, Video Band Width (VBW) filtering and amplitude detection was implemented in a low cost FPGA. The ability to extract the modulating signal from a frequency or amplitude modulated RF signal was also implemented. The same family of FPGA used in the generator design was chosen to be the digital platform for this design. This research makes arguments for the new architecture and then summarises the literature, design considerations, simulation and implementation of the new digital algorithm for the radio frequency spectrum analyser