D/A Resolution Impact on a Poly-phase Multipath Transmitter

In recent publications the Poly-phase multipath technique has been shown to produce a clean output spectrum for a power upconverter (PU) architecture. The technique utilizes frequency independent phase shifts before and after a nonlinear element to cancel out the harmonics and sidebands due to the nonlinearity. A major advantage of this technique is that it circumvents the need to use dedicated RF filters which makes it a potential candidate for cognitive radio transmitters. This paper addresses the requirements on the digital and mixed signal part of such a transmitter. An architecture is proposed based on complex multiplication which can be used to generate the digital multiphase signals required by the multipath technique. Due to equal phase difference of all the paths the same digital hardware could be utilized for carrying out all the phase shifts. When the digital signals pass through a D/A converter which doesn’t have a reconstruction filter, the output in this case would be amplitude discrete like that of a zero order hold. The spectrum of this amplitude discrete signal would have distortion components in it. This can be termed as quantization distortion but now in the context of limited D/A resolution. The multipath technique’s effect on harmonic cancellation, in the presence of such a quantization distortion is explored in this paper. It is shown through simulation that when using ideal phase shifts the multipath technique is able to cancel most of the harmonics produced by an amplitude discrete representation of pure sinusoids. When (upconversion) mixers are used for the second set of phase shifts then with multipath the highest quantization spurs go down with roughly 8db/bit for a single tone and around 10db/bit for two tone inputs

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Arquiteturas paralelas avançadas para transmissores 5G totalmente digitais

The fifth generation of mobile communications (5G) is being prepared and should be rolled out in the early coming years. Massive number of Radio-Frequency (RF) front-ends, peak data rates of 10 Gbps (everywhere and everytime), latencies lower than 10 msec and huge device densities are some of the expected disruptive capabilities. At the same time, previous generations can not be jeopardized, fostering the design of novel flexible and highly integrated radio transceivers able to support the simultaneous transmission of multi-band and multi-standard signals. The concept of all-digital transmission is being pointed out as a promising architecture to cope with such challenging requirements, due to its fully digital radio datapath. This thesis is focused on the proposal and validation of fully integrated and advanced digital transmitter architectures that excel the state-of-the-art in different figures of merit, such as transmission bandwidth, spectral purity, carrier agility, flexibility, and multi-band capability. The first part of this thesis introduces the concept of all-digital RF transmission. In particular, the foundations inherent to this thematic line are given, together with the recent advances reported in the state-of-the-art architectures.The core of this thesis, containing the main developments achieved during the Ph.D. work, is then presented and discussed. The first key contribution to the state-of-the-art is the use of cascaded Delta-Sigma (∆Σ) architectures to relax the analog filtering requirements of the conventional All-Digital Transmitters while maintaining the constant envelope waveform. Then, it is presented the first reported architecture where Antenna Arrays are directly driven by single-chip and single-bit All-Digital Transmitters, with promising results in terms of simplification of the RF front-ends and overall flexibility. Subsequently, the thesis proposes the first reported RF-stage All-Digital Transmitter that can be embedded within a single Field-Programmable Gate Array (FPGA) device. Thereupon, novel techniques to enable the design of wideband All-Digital Transmitters are reported. Finally, the design of concurrent multi-band transmitters is introduced. In particular, the design of agile and flexible dual and triple bands All-DigitalTransmitter (ADT) is demonstrated, which is a very important topic for scenarios that demand carrier aggregation. This Ph.D. contributes withseveral advances to the state-of-the-art of RF all-digital transmitters.A quinta geração de comunicações móveis (5G) está a ser preparada e deve ser comercializada nos próximos anos. Algumas das caracterı́sticas inovadoras esperadas passam pelo uso de um número massivo de font-ends de Rádio-Frequência (RF), taxas de pico de transmissão de dados de 10 Gbps (em todos os lugares e em todas as ocasiões), latências inferiores a 10 mseg e elevadas densidades de dispositivos. Ao mesmo tempo, as gerações anteriores não podem ser ignoradas, fomentando o design de novos transceptores de rádio flexı́veis e altamente integrados, capazes de suportar a transmissão simultânea de sinais multi-banda e multi-standard. O conceito de transmissão totalmente digital é considerado como um tipo de arquitetura promissora para lidar com esses requisitos desafiantes, devido ao seu datapath de rádio totalmente digital. Esta tese é focada na proposta e validação de arquiteturas de transmissores digitais totalmente integradas e avançadas que ultrapassam o estado da arte em diferentes figuras de mérito, como largura de banda de transmissão, pureza espectral, agilidade de portadora, flexibilidade e capacidade multibanda. A primeira parte desta tese introduz o conceito de transmissores de RF totalmente digitais. Em particular, os fundamentos inerentes a esta linha temática são apresentados, juntamente com os avanços mais recentes do estado-da-arte. O núcleo desta tese, contendo os principais desenvolvimentos alcançados durante o trabalho de doutoramento, é então apresentado e discutido. A primeira contribuição fundamental para o estado da arte é o uso de arquiteturas em cascata com moduladores ∆Σ para relaxar os requisitos de filtragem analógica dos transmissores RF totalmente digitais convencionais, mantendo a forma de onda envolvente constante. Em seguida, é apresentada a primeira arquitetura em que agregados de antenas são excitados diretamente por transmissores digitais de um único bit inseridos num único chip, com resultados promissores em termos de simplificação dos front-ends de RF e flexibilidade em geral. Posteriormente, é proposto o primeiro transmissor totalmente digital RF-stage relatado que pode ser incorporado dentro de um único Agregado de Células Lógicas Programáveis. Novas técnicas para permitir o desenho de transmissores RF totalmente digitais de banda larga são também apresentadas. Finalmente, o desenho de transmissores simultâneos de múltiplas bandas é exposto. Em particular, é demonstrado o desenho de transmissores de duas e três bandas ágeis e flexı́veis, que é um tópico essencial para cenários que exigem agregação de múltiplas bandas.Apoio financeiro da Fundação para a Ciência e Tecnologia (FCT) no âmbito de uma bolsa de doutoramento, ref. PD/BD/105857/2014.Programa Doutoral em Telecomunicaçõe

Radio-Communications Architectures

Wireless communications, i.e. radio-communications, are widely used for our different daily needs. Examples are numerous and standard names like BLUETOOTH, WiFI, WiMAX, UMTS, GSM and, more recently, LTE are well-known [Baudoin et al. 2007]. General applications in the RFID or UWB contexts are the subject of many papers. This chapter presents radio-frequency (RF) communication systems architecture for mobile, wireless local area networks (WLAN) and connectivity terminals. An important aspect of today's applications is the data rate increase, especially in connectivity standards like WiFI and WiMAX, because the user demands high Quality of Service (QoS). To increase the data rate we tend to use wideband or multi-standard architecture. The concept of software radio includes a self-reconfigurable radio link and is described here on its RF aspects. The term multi-radio is preferred. This chapter focuses on the transmitter, yet some considerations about the receiver are given. An important aspect of the architecture is that a transceiver is built with respect to the radio-communications signals. We classify them in section 2 by differentiating Continuous Wave (CW) and Impulse Radio (IR) systems. Section 3 is the technical background one has to consider for actual applications. Section 4 summarizes state-of-the-art high data rate architectures and the latest research in multi-radio systems. In section 5, IR architectures for Ultra Wide Band (UWB) systems complete this overview; we will also underline the coexistence and compatibility challenges between CW and IR systems

Design and Implementation of an RF Front-End for Software Defined Radios

Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro­ grammable signal processing devices, giving the radio the ability to change its op­ erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability. Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system. In this thesis, some of major building blocks of a Software defined radio are de­ signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii Abstract algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra­ dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele­ phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation

S-Band QPSK Transmitter for Picosatellites

The small satellite field has become popular amongst academia, amateur satellite (AMSAT) community, and commercial businesses due to the miniaturization of components and smaller form factors. Specifically, the picosatellite structure has gained attraction for its size and affordability of launch fees. However, the size constraint makes it difficult to generate power and limits the transmit power for downlink. Therefore, efficient data modulation is key to providing high data downlink rates. Also, the typical VHF and UHF frequency spectrum used for satellites is getting congested. Hence, the higher frequency bands such as S-band and X-band are gaining attraction and offer higher data bandwidth. To address both issues, an architecture to implement QPSK modulation for S-band operation is proposed. The design is focused on low-power picosatellites and the implementation is targeted for academia and the AMSAT community

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise