89 research outputs found

    A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

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    Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

    Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring

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    Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 μm2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning

    Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier

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    PhD ThesisAs further advances are made in semiconductor manufacturing technology the performance of circuits is continuously increasing. Unfortunately, as the technology node descends deeper into the nanometre region, achieving the potential performance gain is becoming more of a challenge; due not only to the effects of process variation but also to the reduced timing margins between signals within the circuit creating timing problems. Production Standard Automatic Test Equipment (ATE) is incapable of performing internal timing measurements due, first to the lack of accessibility and second to the overall timing accuracy of the tester which is grossly inadequate. To address these issue ‘on-chip’ time measurement circuits have been developed in a similar way that built in self-test (BIST) evolved for ‘on-chip’ logic testing. This thesis describes the design and analysis of three time amplifier circuits. The analysis undertaken considers the operational aspects related to gain and input dynamic range, together with the robustness of the circuits to the effects of process, voltage and temperature (PVT) variations. The design which had the best overall performance was subsequently compared to a benchmark design, which used the ‘buffer delay offset’ technique for time amplification, and showed a marked 6.5 times improvement on the dynamic range extending this from 40 ps to 300ps. The new design was also more robust to the effects of PVT variations. The new time amplifier design was further developed to include an adjustable gain capability which could be varied in steps of approximately 7.5 from 4 to 117. The time amplifier was then connected to a 32-stage tapped delay line to create a reconfigurable time measurement circuit with an adjustable resolution range from 15 down to 0.5 ps and a dynamic range from 480 down to 16 ps depending upon the gain setting. The overall footprint of the measurement circuit, together with its calibration module occupies an area of 0.026 mm2 The final circuit, overall, satisfied the main design criteria for ‘on-chip’ time measurement circuitry, namely, it has a wide dynamic range, high resolution, robust to the effects of PVT and has a small area overhead.Umm Al-Qura University

    Characterization and analysis of process variability in deeply-scaled MOSFETs

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 137-147).Variability characterization and analysis in advanced technologies are needed to ensure robust performance as well as improved process capability. This thesis presents a framework for device variability characterization and analysis. Test structure and test circuit design, identification of significant effects in design of experiments, and decomposition approaches to quantify variation and its sources are explored. Two examples of transistor variability characterization are discussed: contact plug resistance variation within the context of a transistor, and AC, or short time-scale, variation in transistors. Results show that, with careful test structure and circuit design and ample measurement data, interesting trends can be observed. Among these trends are (1) a distinct within-die spatial signature of contact plug resistance and (2) a picosecond-accuracy delay measurement on transistors which reveals the presence of excessive external parasitic gate resistance. Measurement results obtained from these test vehicles can aid in both the understanding of variations in the fabrication process and in efforts to model variations in transistor behavior.by Karthik Balakrishnan.Ph.D

    Study of through-silicon-vias (TSVs) induced transistor variation

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    Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 83-85).As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidth and power efficiency. Through-siliconvias (TSVs), which directly connect stacked structures die-to-die, is one of the key techniques enabling 3D integration. The process steps and physical presence of TSVs, however, may generate a stress-induced thermal mismatch between TSVs and the silicon bulk. These effects could further perturb the performance of nearby electronic structures, particularly transistors, diodes, and associated circuits. This thesis presents a comprehensive study to characterize, analyze and model the impact of TSV-induced stress impact on device and circuit performance and its interaction with polysilicon and shallow-trench-isolation (STI) layout pattern density. A test chip is designed with multiplexing test circuits providing measurements of key parameters of a large number of devices. These devices under test (DUTs) have layouts that explore a range of TSV and device layout choices in the design of experiments (DOEs). The test chip uses a scan chain approach combined with low-leakage and low-variation switches and Kelvin sensing connections, which provide access to detailed analog device characteristics in large arrays of test devices. A test circuit and an Ioff measurement method is designed to perform off-chip wafer probe testing measurement. In addition, a finite element analysis model is constructed to mimic realistic TSV structures and processes. A complete flow and methodology to analyze transistor characteristics and circuit performance under the influence of TSV stress is proposed. An efficient algorithm is also proposed to simulate full-chip circuit variation under the impact of TSV stress based on a grid partition approach. Test cases corresponding to the aforementioned test chip are simulated for comparison with measurement data.by Li Yu.S.M

    Ultra-low Voltage Digital Circuits and Extreme Temperature Electronics Design

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    Certain applications require digital electronics to operate under extreme conditions e.g., large swings in ambient temperature, very low supply voltage, high radiation. Such applications include sensor networks, wearable electronics, unmanned aerial vehicles, spacecraft, and energyharvesting systems. This dissertation splits into two projects that study digital electronics supplied by ultra-low voltages and build an electronic system for extreme temperatures. The first project introduces techniques that improve circuit reliability at deep subthreshold voltages as well as determine the minimum required supply voltage. These techniques address digital electronic design at several levels: the physical process, gate design, and system architecture. This dissertation analyzes a silicon-on-insulator process, Schmitt-trigger gate design, and asynchronous logic at supply voltages lower than 100 millivolts. The second project describes construction of a sensor digital controller for the lunar environment. Parts of the digital controller are an asynchronous 8031 microprocessor that is compatible with synchronous logic, memory with error detection and correction, and a robust network interface. The digitial sensor ASIC is fabricated on a silicon-germanium process and built with cells optimized for extreme temperatures

    Ultra Low Power Circuits for Internet of Things and Deep Learning Accelerator Design with In-Memory Computing

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    Collecting data from environment and converting gathered data into information is the key idea of Internet of Things (IoT). Miniaturized sensing devices enable the idea for many applications including health monitoring, industrial sensing, and so on. Sensing devices typically have small form factor and thus, low battery capacity, but at the same time, require long life time for continuous monitoring and least frequent battery replacement. This thesis introduces three analog circuit design techniques featuring ultra-low power consumption for such requirements: (1) An ultra-low power resistor-less current reference circuit, (2) A 110nW resistive frequency locked on-chip oscillator as a timing reference, (3) A resonant current-mode wireless power receiver and battery charger for implantable systems. Raw data can be efficiently transformed into useful information using deep learning. However deep learning requires tremendous amount of computation by its nature, and thus, an energy efficient deep learning hardware is highly demanded to fully utilize this algorithm in various applications. This thesis also presents a pulse-width based computation concept which utilizes in-memory computing of SRAM.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/144173/1/myungjun_1.pd

    High Resolution/Wideband on-Chip Phase-Shifting

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    A new active LO phase shifter was introduced and implemented in a 2x2 wide band MIMO receiver. The chip was designed with STMicroelectronics 90nm technology. The main advantages of the proposed phase shifter over previous works included a wide band range, high resolution and small area. The phase shifter is based on the dependency of the inverter propagation delay on the load capacitance. Simply, by changing the load capacitance of an inverter, a different propagation delay is generated. A number of these controllable delay cells are cascaded to provide the required phase-shift. In order for the delay cells to reduce the required amount of phase-shifting the I&Q swap circuit is introduced. The I&Q swap circuitry reduces the phase-shifting by one fourth of the original range. The wide band phase shifter is suitable for multi-standard radios, since just one phase shifter is needed to support all standards. This capability of the phase shifter could potentially reduce the size of the die and simplify the design. The measurement shows that the phase shifter is able to provide 360˚ of phase-shifting at the output base band signal when the LO is varying from 1.5GHz to 6GHz. A wider range of the phase shifter is achievable by reducing the capacitance load and increasing the number of cascaded delay cells. The proposed phase shifter is capable of achieving a very high resolution. The resolution of the phase shifter is a function of the inverter current capability and the load capacitance. The measurements show the average resolution of the proposed phase shifter is about 1.32ps. Passive components usually take up a large area on the chip. A MOS capacitor is used as the load to reduce the area of the proposed phase shifter. A method is proposed to improve the phase shifter stability over the temperature and process variations. This method is based on the fact that the propagation delay of an inverter is inversely proportional to the power supply. Therefore, the phase shifters’ power supply must be varied to maintain a relatively constant phase shifter resolution over the temperature and process variations
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