77 research outputs found
Flexible Receivers in CMOS for Wireless Communication
Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block
High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications
Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers.
To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST).
According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance.
If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design.
The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB
Energy-Efficient Wireless Circuits and Systems for Internet of Things
As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications.
This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd
A new vision of software defined radio: from academic experimentation to industrial explotation
The broad objective of this study is to examine the role of Software Defined Radio in an industrial field. Basically examines the changes that have to be done to achieve moving this technology in a commercial domain. It is important to predict the impacts of the introduction of Software Defined Radio in the telecommunications industry because it is a real future that is coming.
The project starts with the evolution of mobile telecommunications systems through the history. Following this, Software Defined Radio is defined and its main features are commented such as its architecture. Moreover, it wants to predict the changes that the telecommunications industry will might suffer with the introduction of SDR and some future structural and organizational variations are suggested. Additionally, it is discussed the positive and negative aspects of the introduction of SDR in the commercial domain from different points of view and finally, the future SDR mobile phone is described with its possible hardware and software.Outgoin
Energy-detection based spectrum sensing for cognitive radio on a real-time SDR platform
There has been an increase in wireless applications due to the technology boom; consequently raising the level of radio spectrum demand. However, spectrum is a limited resource and cannot be infinitely subdivided to accommodate every application. At the same time, emerging wireless applications require a lot of bandwidth for operation, and have seen exponential growth in their bandwidth usage in recent years. The current spectrum allocation technique, proposed by the Federal Communications Commission (FCC) is a fixed allocation technique. This is inefficient as the spectrum is vacant during times when the primary user is not using the spectrum. This strain on the current available bandwidth has revealed signs of an upcoming spectrum crunch; hence the need to find a solution that satisfies the increasing spectrum demand, without compromising the performance of the applications. This work leverages on cognitive radio technology as a potential solution to the spectrum usage challenge. Cognitive radios have the ability to sense the spectrum and determine the presence or absence of the primary user in a particular subcarrier band. When the spectrum is vacant, a cognitive radio (secondary user) can opportunistically occupy the radio spectrum, optimizing the radio frequency band. The effectiveness of the cognitive radio is determined by the performance of the sensing techniques. Known spectrum-sensing techniques are reviewed, which include energy detection, entropy detection, matched-filter detection, and cyclostationary detection. In this dissertation, the energy sensing technique is examined. A real-time energy detector is developed on the Software-Defined Radio (SDR) testbed that is built with Universal Software Radio Peripheral (USRP) devices, and on the GNU Radio software platform. The noise floor of the system is first analysed to determine the detection threshold, which is obtained using the empirical cumulative distribution method. Simulations are carried out using MATrix LABoratory (MATLAB) to set a benchmark. In both simulations and the SDR development platform, an Orthogonal Frequency Division Multiplexing (OFDM) signal with Quadrature Phase Shift Keying (QPSK) modulation is generated and used as the test signal
Longer Term Dynamics of Bit Error Rates using Universal Software Radio Peripheral (USRP) Software Defined Radios for Indoor Environments
Title from PDF of title page viewed August 24, 2017Thesis advisor: Cory BeardVitaIncludes bibliographical references (pages 63-64)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2017In a wireless channel, we encounter several problems like multipath fading,
interference, reduced spectrum efficiency which makes the system less reliable. In our
thesis, we made an analysis of performance of different modulation schemes using
Software Defined Radios. Software Defined Radios provides inexpensive approach for
engineering problems and paves way for its use in academics and research. We
implemented our work using two Universal Software Radio Peripheral kits which are
tested at different environments.
The main advantage of using a Software Defined Radio over the traditional radios
is that they can be reconfigured on the go. Plethora of experiments can be performed on a
single device unlike the traditional device. Owing to its user-friendly nature SDR is being
used by many hobby researchers and academicians.
Our primary goal is to perform an analysis on the usage of SDR with different
modulation schemes and to compare the results of Bit Error Rate Vs Packets Received for
each of the modulation scheme in the indoor environment. For this research, we used GNU
radio as a simulation tool along with the USRP hardware.Introduction -- Software defined radio -- Installation schemes -- Working environments and result
Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity
Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise
gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B.
niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die
Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen
Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der
Fokus der Dissertation liegt auf breitbandigen HF-Frontends für
Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell
verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher
flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines
der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen
Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an
analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von
Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im
Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung
nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter
"Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der
Vorwärtskopplung wird durch intensive Simulationen, Messungen und
Implementierung in realer Hardware verifiziert. Um die Lücken zwischen
Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in
reale Funkmodule zu integrieren, werden verschiedene Untersuchungen
durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das
die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit
alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die
Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen
untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten
Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend
diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales
Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird
gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen
Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter
modulierter Signale sinkt und der Anteil nichtlinear verursachter
Interferenz minimiert wird. Schließlich kann durch das Verfahren die
effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der
zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der
Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der
Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht
auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the
radio's hardware that are largely mutually exclusive, such as low power
consumption, wide bandwidth, and high linearity. Achieving a sufficient
linearity, among other analogue characteristics, is a challenging issue in
practical transceiver design. The focus of this thesis is on wideband
receiver RF front-ends for software defined radio technology, which became
commercially available in the recent years. Practical challenges and
limitations are being revealed in real-world experiments with these radios.
One of the main problems is to ensure a sufficient RF performance of the
front-end over a wide bandwidth. The thesis covers the analysis and
mitigation of receiver non-linearity of typical direct-conversion receiver
architectures, among other RF impairments. The main focus is on DSP-based
algorithms for mitigating non-linearly induced interference, an approach
also known as "Dirty RF" signal processing techniques. The conceived
digital feedforward mitigation algorithm is verified through extensive
simulations, RF measurements, and implementation in real hardware. Various
studies are carried out that bridge the gap between theory and practical
applicability of this approach, especially with the aim of integrating that
technique into real devices. To this end, an advanced baseband behavioural
model is developed that matches to direct-conversion receiver architectures
as close as possible, and thus considers all generated distortions at RF
and baseband. In addition, the algorithm's performance is verified under
challenging fading conditions. Moreover, the thesis presents a
resource-efficient real-time implementation of the proposed solution on an
FPGA. Finally, different use cases are covered in the thesis that includes
spectrum monitoring or sensing, GSM downlink reception, and GSM-based
passive radar. It is shown that non-linear distortions can be successfully
mitigated at system level in the digital domain, thereby decreasing the bit
error rate of distorted modulated signals and reducing the amount of
non-linearly induced interference. Finally, the effective linearity of the
front-end is increased substantially. Thus, the proper operation of a
low-cost radio under presence of receiver non-linearity is possible. Due to
the flexible design, the algorithm is generally applicable for wideband
receivers and is not restricted to software defined radios
Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas
This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next
generation 5G wireless network structure will be heterogeneous, the device
density and their mobility will increase and massive MIMO connectivity
capability will be widespread, the main investigated problem is formulated –
increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks.
The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes.
The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the
introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included.
The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation.
The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions.
The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and
measurement results for all designed radio frequency power amplifiers.
General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation.
5 papers, focusing on the subject of the discussed dissertation, have been
published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made
9 presentations at 9 scientific conferences at a national and international level.Dissertatio
Adaptive multilevel quadrature amplitude radio implementation in programmable logic
Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise
ratios due to bit errors and packet retransmission. To obtain a more “robust” physical
layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions.
This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in “burst” mode, and can reliably synchronize to different QAM constellations “burst-by-burst”.
Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of
which are becoming popular for highly integrated, cost-effective wireless transceivers
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