Flash-based security primitives: Evolution, challenges and future directions

Over the last two decades, hardware security has gained increasing attention in academia and industry. Flash memory has been given a spotlight in recent years, with the question of whether or not it can prove useful in a security role. Because of inherent process variation in the characteristics of flash memory modules, they can provide a unique fingerprint for a device and have thus been proposed as locations for hardware security primitives. These primitives include physical unclonable functions (PUFs), true random number generators (TRNGs), and integrated circuit (IC) counterfeit detection. In this paper, we evaluate the efficacy of flash memory-based security primitives and categorize them based on the process variations they exploit, as well as other features. We also compare and evaluate flash-based security primitives in order to identify drawbacks and essential design considerations. Finally, we describe new directions, challenges of research, and possible security vulnerabilities for flash-based security primitives that we believe would benefit from further exploration

An efficient unused integrated circuits detection algorithm for parallel scan architecture

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm

A Non-invasive Technique to Detect Authentic/Counterfeit SRAM Chips

Many commercially available memory chips are fabricated worldwide in untrusted facilities. Therefore, a counterfeit memory chip can easily enter into the supply chain in different formats. Deploying these counterfeit memory chips into an electronic system can severely affect security and reliability domains because of their sub-standard quality, poor performance, and shorter lifespan. Therefore, a proper solution is required to identify counterfeit memory chips before deploying them in mission-, safety-, and security-critical systems. However, a single solution to prevent counterfeiting is challenging due to the diversity of counterfeit types, sources, and refinement techniques. Besides, the chips can pass initial testing and still fail while being used in the system. Furthermore, existing solutions focus on detecting a single counterfeit type (e.g., detecting recycled memory chips). This work proposes a framework that detects major counterfeit static random-access memory (SRAM) types by attesting/identifying the origin of the manufacturer. The proposed technique generates a single signature for a manufacturer and does not require any exhaustive registration/authentication process. We validate our proposed technique using 345 SRAM chips produced by major manufacturers. The silicon results show that the test scores ($F_{1}$ score) of our proposed technique of identifying memory manufacturer and part-number are 93% and 71%, respectively.Comment: This manuscript has been submitted for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessibl

Hardware Trojan Detection on a PCB Through Differential Power Monitoring

There is a general consensus that contemporary electronics are at risk of cyber-attacks or malicious modifications, such as Hardware Trojans (HT). This makes it crucial to develop reliable countermeasures at both Integrated Circuit (IC) and Printed Circuit Board (PCB) levels. While HT detection at IC level has been widely studied in the past several years, there is still very limited research carried out to tackle HTs on PCBs. We propose a power analysis method for detecting HT components implanted on PCBs. An experimental setup, using a hardware prototype, is built and tested for verification of the methodology, taking process and temperature variations into account. The results confirm the ability to detect alien components on a PCB and provide directions for further research. The performance degradation of the original PCB due to the implementation of the proposed approach is negligible. The area overhead of the proposed method is small, related to the original PCB design, and consists of Sub Power Monitors of individual ICs on the PCB and Main Power Monitor for the overall power measurement of the PCB. To the best of our knowledge this research is the first to develop a PCB HT detection methodology using power analysis

EMI measurement and modeling techniques for complex electronic circuits and modules

This dissertation consists of four papers. In the first paper, a combined model for predicting the most critical radiated emissions and total radiated power due to the display signals in a TV by incorporating the main processing board using the Huygens Equivalence theorem and the radiation due to the flex cable based on active probe measurements was developed. In the second paper, a frequency-tunable resonant magnetic field probe was designed in the frequency range 900-2260 MHz for near-field scanning applications for the radio frequency interference studies by using a varactor diode providing the required capacitance and the parasitic inductance of a magnetic field loop (i.e., a parallel LC circuit). Measurement results showed good agreement with the simulated results. In the third paper, a wideband microwave method was developed as a means for rapid detection of slight dissimilarities (including counterfeit) and aging effects in integrated circuits (ICs) based on measuring the complex reflection coefficient of an IC when illuminated with an open-ended rectangular waveguide probe, at K-band (18-26.5 GHz) and Ka-band (26.5-40 GHz) microwave frequencies. In the fourth paper, a method to predict radiated emissions from DC-DC converters with cables attached on the input side to a LISN and on the output side to a DC brushless motor as load based on linear terminal equivalent circuit modeling was demonstrated. The linear terminal equivalent model was extracted using measured input and output side common mode currents for various characterization impedances connected at the input and output terminals of the converter --Abstract, page iv

Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design

The continued scaling of VLSI circuits has provided a wealth of opportunities andchallenges to the VLSI circuit design area. Both these challenges and opportunities, however,require new simulation tools that can enable their solution or exploitation as classicalmethods typically dealt with problem domains with smaller scales or less complexity. Inthis dissertation, simulation methods are presented to address the emerging VLSI designtopics of Electromigration induced aging and Ising computing and are then applied to theapplication areas of hardware security and graph partitioning respectively.The Electromigration aging effect in VLSI circuits is a long-term reliability issueaffecting current carrying metal wires leading to IR drop degradation. Typically, simpleanalytical equations can determine a wire’s effective age or if it will be affected by the EMaging effect at all. However, these classical methods are overly conservative and can lead toover design or unnecessary design iterations. Furthermore, it is expected that the EM agingeffect will become more severe in future Integrated Cirucits (ICs) due to increasing currentdensities and the prevalance of polycrystaline copper atom structures seen at small wiredimensions. For this reason, more comprehensive simulation techniques that can efficientlysimulate the EM effect with less conservative results can help mitigate overdesign andincrease design margins while reducing design iterations.The area of Hardware Security is becoming increasingly important as the chipsupply chain becomes more globalized and the integrity of chips becomes more diffiuclt toverify. Utilizing the accurate simulation techniques for EM, we can utilize this reliabilityeffect to demonstrate how a reliability based attack could be perpatrated. Furthermore, wecan utilize this aging effect as a defense mechanism to help us validate the integrity of anIC and detect counterfeit chips in the component supply chain market.Ising computing is an emerging method of solving combinatorial optimization problemsby simulating the interactions of so-called spin glasses and their interactions. Borrowingconcepts from quantum computing, this methods mimics the quantum interaction betweenspin glasses in such a way that finding a ground state of these spin glass models leadsto the solution of a particular problem. In this dissertation, effective methods of simulatingthe spin glass interactions using General Purpose Graphics Processing Units (GPGPUs)and finding their ground state are developed.In addition to the GPU based Ising model simulations, important combinatorialproblems can be mapped to the Ising model. In this dissertation the Ising solver is appliedto graph partitioning which can be utilized in VLSI design and many other domains as well.Specifically, solvers for the maxcut problem and the balanced min-cut partitioning problemare developed