Generating All Two-MOS-Transistor Amplifiers Leads to New Wide-Band LNAs

This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that MOSFET is exploited as a voltage-controlled current source. This leads to new circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band LNA has been designed in 0.35-µm CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V

Thermal Noise Canceling in LNAs: A Review

Most wide-band amplifiers suffer from a fundamental trade-off between noise figure NF and source impedance matching, which limits NF to values typically above 3dB. Recently, a feed-forward noise canceling technique has been proposed to break this trade-off. This paper reviews the principle of the technique and its key properties. Although the technique has been applied to wideband CMOS LNAs, it can just as well be implemented exploiting transconductance elements realized with other types of transistors

Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends

Fully Integrated Frequency and Phase Generation for a 6-18GHz Tunable Multi-Band Phased-Array Receiver in CMOS

Fully integrated frequency-phase generators for a 6-18GHz wide-band phased-array receiver element are presented that generate 5-7GHz and 9-12GHz first LO signals with less than -95dBc/Hz phase noise at 100kHz offset. Second LO signals with digitally controllable fourquadrant phase- and amplitude spread with better than 3° resolution are generated and allow removal of systematic reference clock skew as well as accurate selection of the received signal phase. This frequency- and phase generation scheme was successfully demonstrated in a 6-18GHz receiver system configured as an electrical 4-element array

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

Theory Based on Device Current Clipping to Explain and Predict Performance Including Distortion of Power Amplifiers for Wireless Communication Systems

Power amplifiers are critical components in wireless communication systems that need to have high efficiency, in order to conserve battery life and minimise heat generation, and at the same time low distortion, in order to prevent increase of bit error rate due to constellation errors and adjacent channel interference. This thesis is aimed at meeting a need for greater understanding of distortion generated by power amplifiers of any technology, in order to help designers manage better the trade-off between obtaining high efficiency and low distortion. The theory proposed in this thesis to explain and predict the performance of power amplifiers, including distortion, is based on analysis of clipping of the power amplifier device current, and it is a major extension of previous clipping analyses, that introduces many key definitions and concepts. Distortion and other power amplifier metrics are determined in the form of 3-D surfaces that are plotted against PA class, which is determined by bias voltage, and input signal power level. It is shown that the surface of distortion exhibits very high levels due to clipping in the region where efficiency is high. This area of high distortion is intersected by a valley that is ‘L’-shaped. The 'L'-shaped valley is subject to a rotation that depends on the softness of the cut-off of the power amplifier device transfer characteristic. The distortion surface with rotated 'L'-shaped valley leads to predicted curves for distortion versus input signal power that match published measured curves for power amplifiers even using very simple device models. The distortion versus input signal power curves have types that are independent of technology. In class C, there is a single deep null. In the class AB range, that is divided into three sub-ranges, there may be two deep nulls (sub-range AB(B)), a ledge (sub-range AB(A)) or a shallow null with varying depth (sub-range AB(AB))

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB