46 research outputs found

    Desarrollo de un kernel académico para arquitecturas x86-64 en C++

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    El siguiente trabajo tiene como objetivo el desarrollo y documentación de alma, un kernel (núcleo) en C++ de funcionalidad muy reducida para manejar los recursos hardware de una máquina con arquitectura x86-64. En sus últimas versiones, alma puede ser arrancado en hardware real mediante un archivo iso, tanto en sistemas con UEFI como con BIOS. Al tratarse de un kernel no se dispone de biblioteca estándar, funciones base o llamadas a sistema (syscalls) sobre las que desarrollar. Cada píxel que aparece por pantalla, cada acción de los pistones del teclado, cada reserva de memoria: está todo gestionado exclusivamente por el kernel y plasmado en este trabajo. Para mejorar la calidad del software desarrollado se han implementado desde cero funciones conocidas como printf, malloc, scanf, etc. En conjunto con el kernel también se ha desarrollado un bootloader capaz de arrancar alma en máquinas que dispongan de UEFI. Se ha escrito en el lenguaje C junto con la librería de desarrollo posix-uefi [1] para comunicarnos con los servicios de UEFI mediante una interfaz POSIX. En las últimas versiones del proyecto, el desarrollo del bootloader ha sido reemplazado por la integración del protocolo de arranque stivale2 en el kernel. Ahora alma puede ser arrancado por cualquier bootloader que implemente el mismo protocolo. También se proporciona un sistema de construcción con cmake [2] capaz de compilar el proyecto de forma automatizada. Junto al sistema de construcción, se ha desarrollado un script capaz de construir gcc y otros programas de la toolchain del proyecto con las modificaciones necesarias para desarrollar un kernel. Puesto que construir alma es una tarea muy compleja, se ha configurado un entorno de desarrollo virtualizado preparado para construir el proyecto. El objetivo del proyecto no es desarrollar un kernel usable en hardware real ni útil para determinadas tareas. alma ha sido desarrollado con fines meramente académicos, al igual que otros proyectos similares desarrollados por otras universidades tales como xv6 [3] (Massachusetts Institute of Technology), OS/161 [4] (Harvard) y SWEB [5] (Graz University of Technology)

    Неразрушающее тестирование запоминающих устройств на базе двойных адресных последовательностей

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    An effectiveness of the application of classical non-destructive tests for testing storage devices and their main disadvantages, among which there are great time complexity and low diagnostic ability, are analysed. The concept of double address sequence 2A is defined and the examples of their formation based on counter address sequences and Gray code are provided. The basic element of non-destructive tests with the use of double address sequences is synthesized and its detecting and diagnostic abilities for different storage devices defects are explored. There are two new non-destructive tests of memory devices March_2A_1 and March_2A_2 and an estimation of their time complexity and efficiency of failure detection are given. A significantly lower time complexity of the proposed tests and their high diagnostic ability in comparison with classical non-destructive tests are shown.Анализируется эффективность применения классических неразрушающих тестов для тестирования запоминающих устройств (ЗУ) и их основные недостатки, среди которых выделяют большую временную сложность и низкую диагностическую способность. Определяется понятие двойной адресной последовательности 2A и приводятся примеры их формирования на базе счетчиковых адресных последовательностей и последовательностей кода Грея. Синтезируется базовый элемент неразрушающих тестов с применением двойных адресных последовательностей и исследуются его обнаруживающая и диагностическая способности для различных неисправностей ЗУ. Приводятся два новых неразрушающих теста ЗУ March_2А_1 и March_2А_2, для которых оценивается их временная сложность и эффективность обнаружения неисправностей ЗУ. Показывается существенно меньшая временная сложность предложенных тестов и высокая диагностическая способность по сравнению с классическими неразрушающими тестами

    Cellular Automata

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    Modelling and simulation are disciplines of major importance for science and engineering. There is no science without models, and simulation has nowadays become a very useful tool, sometimes unavoidable, for development of both science and engineering. The main attractive feature of cellular automata is that, in spite of their conceptual simplicity which allows an easiness of implementation for computer simulation, as a detailed and complete mathematical analysis in principle, they are able to exhibit a wide variety of amazingly complex behaviour. This feature of cellular automata has attracted the researchers' attention from a wide variety of divergent fields of the exact disciplines of science and engineering, but also of the social sciences, and sometimes beyond. The collective complex behaviour of numerous systems, which emerge from the interaction of a multitude of simple individuals, is being conveniently modelled and simulated with cellular automata for very different purposes. In this book, a number of innovative applications of cellular automata models in the fields of Quantum Computing, Materials Science, Cryptography and Coding, and Robotics and Image Processing are presented

    VLSI Design

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    This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

    REDUCING POWER DURING MANUFACTURING TEST USING DIFFERENT ARCHITECTURES

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    Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test. In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We group the control bits together into one or more control chains. To address the extra pin(s) required to shift data into the control chain(s) and significant post processing in the first architecture, we explored a second architecture. The second architecture stitches the control bits into the chains they control as EECBs (embedded enable capture bits) in between the segments. This allows an ATPG software tool to automatically generate the appropriate EECB values for each pattern to maintain the fault coverage. This also works in the presence of an on-chip decompressor. The last architecture focuses primarily on the self-test of a device in a 3D stacked IC when an existing FPGA in the stack can be programmed as a tester. We show that the energy expended during test is significantly less than would be required using low power patterns fed by an on-chip decompressor for the same very short scan chains

    FPGA ARCHITECTURE AND VERIFICATION OF BUILT IN SELF-TEST (BIST) FOR 32-BIT ADDER/SUBTRACTER USING DE0-NANO FPGA AND ANALOG DISCOVERY 2 HARDWARE

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    The integrated circuit (IC) is an integral part of everyday modern technology, and its application is very attractive to hardware and software design engineers because of its versatility, integration, power consumption, cost, and board area reduction. IC is available in various types such as Field Programming Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), System on Chip (SoC) architecture, Digital Signal Processing (DSP), microcontrollers (μC), and many more. With technology demand focused on faster, low power consumption, efficient IC application, design engineers are facing tremendous challenges in developing and testing integrated circuits that guaranty functionality, high fault coverage, and reliability as the transistor technology is shrinking to the point where manufacturing defects of ICs are affecting yield which associates with the increased cost of the part. The competitive IC market is pressuring manufactures of ICs to develop and market IC in a relatively quick turnaround which in return requires design and verification engineers to develop an integrated self-test structure that would ensure fault-free and the quality product is delivered on the market. 70-80% of IC design is spent on verification and testing to ensure high quality and reliability for the enduser. To test complex and sophisticated IC designs, the verification engineers must produce laborious and costly test fixtures which affect the cost of the part on the competitive market. To avoid increasing the part cost due to yield and test time to the end-user and to keep up with the competitive market many IC design engineers are deviating from complex external test fixture approach and are focusing on integrating Built-in Self-Test (BIST) or Design for Test (DFT) techniques onto IC’s which would reduce time to market but still guarantee high coverage for the product. Understanding the BIST, the architecture, as well as the application of IC, must be understood before developing IC. The architecture of FPGA is elaborated in this paper followed by several BIST techniques and applications of those BIST relative to FPGA, SoC, analog to digital (ADC), or digital to analog converters (DAC) that are integrated on IC. Paper is concluded with verification of BIST for the 32-bit adder/subtracter designed in Quartus II software using the Analog Discovery 2 module as stimulus and DE0-NANO FPGA board for verification

    Radar Technology

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    In this book “Radar Technology”, the chapters are divided into four main topic areas: Topic area 1: “Radar Systems” consists of chapters which treat whole radar systems, environment and target functional chain. Topic area 2: “Radar Applications” shows various applications of radar systems, including meteorological radars, ground penetrating radars and glaciology. Topic area 3: “Radar Functional Chain and Signal Processing” describes several aspects of the radar signal processing. From parameter extraction, target detection over tracking and classification technologies. Topic area 4: “Radar Subsystems and Components” consists of design technology of radar subsystem components like antenna design or waveform design

    Self-Test Mechanisms for Automotive Multi-Processor System-on-Chips

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    L'abstract è presente nell'allegato / the abstract is in the attachmen
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