Method for Testing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. This is followed by the steps of initiating the built-in self-test, generating test patterns with the programmable logic blocks and analyzing a resulting response to produce a pass/fail indication with the programmable logic blocks. More specifically, the configuring step includes establishing a first group of programmable logic blocks as test pattern generators and output response analyzers and a second group of programmable logic blocks as blocks under test. The blocks under test are then repeatedly recongifured in order to completely test each block under test in all possible modes of operation. The programming of the first and second groups of programmable logic blocks is then reversed and the testing of each new block under test is then completed

Method of Testing and Diagnosing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes establishing a first group of programmable logic blocks as test pattern generators or output response analyzers and a second group of programmable logic blocks as blocks under test. This is followed by generating test patterns and comparing outputs of two blocks under test with one output response analyzer. Next is the combining of results of a plurality of output response analyzers utilizing an iterative comparator in order to produce a pass/fail indication. The method also includes the step of reconfiguring each block under test so that each block under test is tested in all possible modes of operation. Further, there follows the step of reversing programming of the groups of programmable logic blocks so that each programmable logic block is configured at least once as a block under test

Method for Testing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. Specifically, the FPGA under test may be configured to act as an iterative logic array wherein a first group of programmable logic blocks are configured as test pattern generators, output response analyzers and helper cells, and a second group of programmable logic blocks are configured as blocks under test. The blocks under test are then repeatedly reconfigured in order to completely test each block under test in all possible modes of operation. The first and second groups of programmable logic blocks are then repeatedly rearranged so that all the programmable logic blocks are established as blocks under test at least once. Following the rearrangement, the repeated reconfiguration of the blocks under test is performed once again

Built in self test for RAM using VHDL

This project emphasized mainly on software analysis. Modelsim-Altera 6.4a is the software that used to generate every single module of the Built-in-Self-Test (BIST) for Random access Memory (RAM) architecture. There are three key things to be concern in the BIST for RAM which is the Test Pattern Generator (TPG), Output Response Analysis (ORA) and RAM. The output of counter which is a type of TPG is analyzed to provide a pattern for March test algorithm. At the mean time, the ORA compare the output from decoder and the RAM output itself which modeled under the theory of numerical autonomy of error vectors from the circuit under test. The output of ORA, the comparator, will show pass or fail for faulty detection of RAM. The system has been successfully developed and vector waveform is used to examine the result of the system. From the result obtained, it showed that the system is working as expected with satisfactory result

REDUCING POWER DURING MANUFACTURING TEST USING DIFFERENT ARCHITECTURES

Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test. In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We group the control bits together into one or more control chains. To address the extra pin(s) required to shift data into the control chain(s) and significant post processing in the first architecture, we explored a second architecture. The second architecture stitches the control bits into the chains they control as EECBs (embedded enable capture bits) in between the segments. This allows an ATPG software tool to automatically generate the appropriate EECB values for each pattern to maintain the fault coverage. This also works in the presence of an on-chip decompressor. The last architecture focuses primarily on the self-test of a device in a 3D stacked IC when an existing FPGA in the stack can be programmed as a tester. We show that the energy expended during test is significantly less than would be required using low power patterns fed by an on-chip decompressor for the same very short scan chains

Fault-Tolerant Computing: An Overview

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNASA / NAG-1-613Semiconductor Research Corporation / 90-DP-109Joint Services Electronics Program / N00014-90-J-127

Неразрушающее тестирование запоминающих устройств на базе двойных адресных последовательностей

An effectiveness of the application of classical non-destructive tests for testing storage devices and their main disadvantages, among which there are great time complexity and low diagnostic ability, are analysed. The concept of double address sequence 2A is defined and the examples of their formation based on counter address sequences and Gray code are provided. The basic element of non-destructive tests with the use of double address sequences is synthesized and its detecting and diagnostic abilities for different storage devices defects are explored. There are two new non-destructive tests of memory devices March_2A_1 and March_2A_2 and an estimation of their time complexity and efficiency of failure detection are given. A significantly lower time complexity of the proposed tests and their high diagnostic ability in comparison with classical non-destructive tests are shown.Анализируется эффективность применения классических неразрушающих тестов для тестирования запоминающих устройств (ЗУ) и их основные недостатки, среди которых выделяют большую временную сложность и низкую диагностическую способность. Определяется понятие двойной адресной последовательности 2A и приводятся примеры их формирования на базе счетчиковых адресных последовательностей и последовательностей кода Грея. Синтезируется базовый элемент неразрушающих тестов с применением двойных адресных последовательностей и исследуются его обнаруживающая и диагностическая способности для различных неисправностей ЗУ. Приводятся два новых неразрушающих теста ЗУ March_2А_1 и March_2А_2, для которых оценивается их временная сложность и эффективность обнаружения неисправностей ЗУ. Показывается существенно меньшая временная сложность предложенных тестов и высокая диагностическая способность по сравнению с классическими неразрушающими тестами

An efficient design of embedded memories and their testability analysis using Markov chains

This article presents a design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM) where neither are the address, read/write and data input lines directly controllable nor are the data output lines externally observable. Unlike the conventional approaches, which frequently employ on-chip circuits such as linear feedback shift register (LFSR), data registers and multibit comparator for verifying the response of the memory-under-test (MUT) with the reference signature of a fault-free gold unit , the proposed technique uses an efficient testable design, which helps accelerate test algorithms by a factor of 0.5√ n , if the RAM is organized into an n ×1 array and improve the test reliability by eliminating the LFSR that is known to have aliasing problems. Another serious problem in embedded memory testing by random test patterns is the problem of memory initialization, which has been tackled here by adding word-line flag registers. The paper has made indepth empirical studies of the functional faults such as stuck-at, coupling, and pattern-sensitive by suitably representing these faults by Markov chains and by simulating these chains to derive various test lengths required for detecting these faults. The simulation results conclusively show that, in order to test a IM-bit RAM for detecting the common functional faults, the proposed technique needs only one second as opposed to about an hour needed by the conventional random testing where memory cells are tested sequentially.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43013/1/10836_2004_Article_BF00134733.pd