2 research outputs found
Multivalued Logic Circuit Design for Binary Logic Interface
Binary logic and devices have been in used since inception with advancement
and technology and millennium gate design era. The development in binary logic
has become tedious and cumbersome. Multivalued logic enables significant more
information to be packed within a single digit. The design and development of
logic circuit becomes very compact and easier. Attempts are being made to
fabricate multivalued logic based devices. Since present devices can be
implemented only in binary system,it is necessary to evolve a system that can
built the circuit in multivalued logic system and convert in binary logic
system. In multivalued logic system logic gates differ in different logic
system, a quaternary has become mature in terms of logic algebra and gates.
Hence logic design based on above system can be done using standard procedure.
In this dissertation a logic circuit design entry based on multivalued logic
system has been taken up that can provide the ease of circuit design in
multivalued system and output as binary valued circuit. The named "MVL-DEV"
offers editing, storage and conversion into binary facility.Comment: 72 pages,Dissertation Repor
Application-Specific Number Representation
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), enable application-
specific number representations. Well-known number formats include fixed-point, floating-
point, logarithmic number system (LNS), and residue number system (RNS). Such different
number representations lead to different arithmetic designs and error behaviours, thus produc-
ing implementations with different performance, accuracy, and cost.
To investigate the design options in number representations, the first part of this thesis presents
a platform that enables automated exploration of the number representation design space. The
second part of the thesis shows case studies that optimise the designs for area, latency or
throughput from the perspective of number representations.
Automated design space exploration in the first part addresses the following two major issues:
² Automation requires arithmetic unit generation. This thesis provides optimised
arithmetic library generators for logarithmic and residue arithmetic units, which support
a wide range of bit widths and achieve significant improvement over previous designs.
² Generation of arithmetic units requires specifying the bit widths for each
variable. This thesis describes an automatic bit-width optimisation tool called R-Tool,
which combines dynamic and static analysis methods, and supports different number
systems (fixed-point, floating-point, and LNS numbers).
Putting it all together, the second part explores the effects of application-specific number
representation on practical benchmarks, such as radiative Monte Carlo simulation, and seismic
imaging computations. Experimental results show that customising the number representations
brings benefits to hardware implementations: by selecting a more appropriate number format,
we can reduce the area cost by up to 73.5% and improve the throughput by 14.2% to 34.1%; by
performing the bit-width optimisation, we can further reduce the area cost by 9.7% to 17.3%.
On the performance side, hardware implementations with customised number formats achieve
5 to potentially over 40 times speedup over software implementations