A Survey on Application Specific Processor Architectures for Digital Hearing Aids

On the one hand, processors for hearing aids are highly specialized for audio processing, on the other hand they have to meet challenging hardware restrictions. This paper aims to provide an overview of the requirements, architectures, and implementations of these processors. Special attention is given to the increasingly common application-specific instruction-set processors (ASIPs). The main focus of this paper lies on hardware-related aspects such as the processor architecture, the interfaces, the application specific integrated circuit (ASIC) technology, and the operating conditions. The different hearing aid implementations are compared in terms of power consumption, silicon area, and computing performance for the algorithms used. Challenges for the design of future hearing aid processors are discussed based on current trends and developments

A study on wireless hearing aids system configuration and simulation

Master'sMASTER OF SCIENC

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements

Efficient audio signal processing for embedded systems

We investigated two design strategies that would allow us to efficiently process audio signals on embedded systems such as mobile phones and portable electronics. In the first strategy, we exploit properties of the human auditory system to process audio signals. We designed a sound enhancement algorithm to make piezoelectric loudspeakers sound "richer" and "fuller," using a combination of bass extension and dynamic range compression. We also developed an audio energy reduction algorithm for loudspeaker power management by suppressing signal energy below the masking threshold. In the second strategy, we use low-power analog circuits to process the signal before digitizing it. We designed an analog front-end for sound detection and implemented it on a field programmable analog array (FPAA). The sound classifier front-end can be used in a wide range of applications because programmable floating-gate transistors are employed to store classifier weights. Moreover, we incorporated a feature selection algorithm to simplify the analog front-end. A machine learning algorithm AdaBoost is used to select the most relevant features for a particular sound detection application. We also designed the circuits to implement the AdaBoost-based analog classifier.PhDCommittee Chair: Anderson, David; Committee Member: Hasler, Jennifer; Committee Member: Hunt, William; Committee Member: Lanterman, Aaron; Committee Member: Minch, Bradle

Bezprzewodowa Jednostka Audio

Mestrado em Engenharia ElectrónicaA presente tese pretende descrever o desenvolvimento de um sistema electrónico, cuja funcionalidade se baseia na transmissão de sinais áudio através da rede Wireless. Inicialmente foi estudada a família de microcontroladores PIC32, no qual se incluiu a sua forma de programação. Foi ainda realizada pesquisa acerca dos possíveis métodos de compressão de áudio, culminando com o desenvolvimento de algoritmos de compressão no software MATLAB. Seguidamente foi desenvolvida a PIC32 Module – daughterboard do projecto. Esta é uma componente universal que contém um microcontrolador PIC32, de fácil utilização em outros projectos. Posteriormente foi criado o dispositivo Wireless Audio Unit – o objectivo basilar desta tese. Este passo compreendeu a esquematização e PCB de ambas as partes: o transmissor e o receptor. Após a montagem, ambos os dispositivos forma colocados em caixas. O firmware dos dois microcontroladores PIC32 foi criado em linguagem de programação C. O ADC e o DAC são controlados pelo firmware do PIC32, estando a ser executadas correctamente as suas funções. No momento do desenvolvimento da componente escrita desta tese, ainda se mantêm alguns problemas associados à manipulação do transceptor. Por esta razão, o firmware WAU não foi terminado, e o dispositivo não cumpre, ainda, a sua funcionalidade.The thesis aims to report on the development of an electronic system, which task is to transmit wirelessly an audio signal. The work was started by studying the PIC32 family of microcontrollers including the way of programming. The research on audio compression methods that was made, finished with development of compression algorithms in MATLAB software. Following, the PIC32 Module – the daughterboard of project was designed. This part is universal unit containing PIC32 microcontroller, which could be easily used in many other projects. Afterwards, it was created the proper Wireless Audio Unit device – the main objective of this dissertation. This step included design of schematics and PCB for two its parts: transmitter and receiver. After assembling, both devices was put into enclosures. The firmware for two PIC32 microcontrollers was created in C programming language. The ADC and DAC are controlled by PIC32 firmware and are correctly realizing their functions. At the moment of writing this document, the problem with handling transceiver was not solved. For this reason the firmware WAU was not finished and the device does not have its functionality.Celem niniejszego dokumentu jest opis wykonanego systemu elektronicznego, którego zadaniem jest bezprzewodowa transmisja sygnału audio. Praca została rozpoczęta od zapoznania się z rodziną mikrokontrolerów PIC32, włączając w to poznanie metod ich programowania. Badania nad istniejącymi metodami kompresji audio, zostały uwieńczone opracowaniem algorytmów kompresji w oprogramowaniu MATLAB. Następnie został zaprojektowany moduł rozszerzenia - PIC32 Module. Jest to uniwersalna jednostka zawierająca mikrokontroler PIC32, która może być łatwo wykorzystana również w innych projektach. Kolejnym krokiem było stworzenie właściwego urządzenia – Wireless Audio Unit (Bezprzewodowa Jednostka Audio), będącego głównym celem tej pracy. Etap ten zawierał projekt schematu oraz płytki obwodu drukowanego dwóch części projektu: WAU Transmitter (Nadajnik) i WAU Receiver (odbiornik). Po montażu, oba urządzenia zostały umieszczone w obudowach. Oprogramowanie dla mikrokontrolerów PIC32 zostało stworzone w języku programowania C. Przetworniki a/c oraz c/a są kontrolowane przez mikrokontroler i poprawnie realizują swoje funkcje. W chwili powstawania tego raportu, problem z obsługą transceivera nie został rozwiązany. Z tego powodu, oprogramowanie dla mikrokontrolerów nie zostało ukończone i urządzenie nie posiada założonej funkcjonalności