An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole-zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity-gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130-nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single-pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches

Indirect Compensation Techniques for Three-Stage Fully-Differential Op-Amps

As CMOS technology continues to evolve, thesupply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology is then extended to the design of three-stage fully-differential op-amps. Novel three-stage fully-differential gain-stage cascade structures are presented with efficient common mode feedback (CMFB) stabilization. Simulation results are presented for the designed RNIC fullydifferential three-stage op-amps. The fully-differential three-stage op-amps, designed in 0.5 μm CMOS, typically exhibit 18 MHz unity-gain frequency, 82 dB open-loop DC gain, nearly 300 ns transient settling and 72° phase-margin for a 500 pF load

Indirect Compensation Techniques for Three-Stage CMOS Op-Amps

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100ns transient settling and 72° phase-margin for 500pF load. This results in significantly higher op-amp performance metrics over the traditional op-amp designs while at the same time having smaller layout area

The role of group values in the relationship between group faultlines and performance

This study explores the moderating effects of group values on the relationship between group faultlines and performance. Faultlines occur when group members align along two or more different demographic characteristics causing a group to split into homogeneous subgroups (adapted from Lau and Murnighan, 1998). We theorize and empirically examine three group values variables: career-, change-, and task-specificity. Analyses are performed on 81 work groups from a Fortune 500 information processing firm. Two levels of performance are considered in connection with group faultlines: individual performance (performance ratings) and group performance (bonuses and stock options). Our results provide support for our model of group values, faultiness and performance

A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

In this paper, a simple while effective methodology to calculate the symbolic transfer function of a multistage amplifier with frequency compensation is proposed. Three general amplifier models are introduced and analyzed, which represent basic topologies found in the literature. For these amplifier models, the symbolic transfer function is derived and specific strategies for the zero and non-dominant pole expressions are presented. The methodology is suited for hand calculations and yields accurate results while offering more intuition into the operation of the widely adopted frequency compensation solutions discussed in the literature. The effectiveness of the proposed approach is validated through various typical cases of study

Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

Multipath Miller Compensation for Switched-Capacitor Systems

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator

Can you hear me now? The moderating effects of procedural justice within consumer-brand relationships

Consumer-brand relationships have led consumers to expect fair outcomes (i.e., distributive justice) consistent with their relationship norms with a brand. Deviation from these norms produced intuitive consequences such as a reduction of consumer loyalty and trust towards the brand. Yet, 65-85% of consumers still counterintuitively defect to a brand’s competitor. According to consumers, aspects of procedural justice qualitatively appeared to be major components that affected their attitudes towards brands. However, the effect of this construct within relationship norms has been underexamined, producing an empirical gap. The purpose of this dissertation was to bridge this gap by identifying the effect procedural justice has on consumer loyalty and trust within different consumer-brand relationships. In pursuit of this purpose, three studies were conducted. The first two studies examined how consumer-brand relationships influenced the perception of procedural justice. Study 1 replicated previous research. Procedural justice affected participants’ loyalty and trust similarly, while distributive justice affected them depending on their relationship with a brand. Study 2 addressed limitations within Study 1 and produced conflicting results. Study 2 found that positive brand relationships were associated with a larger change in loyalty and trust as perceptions of procedural justice increased compared to negative relationships. To address the conflicting evidence of Study 1 and Study 2, Study 3 examined initial and post consumers’ expectations of consistent or inconsistent procedural information in relation to their brand relationship to produce changes in consumer loyalty and trust. Inconsistent performance of procedural justice resulted in no change in consumer loyalty and trust. Yet regular performance of these inconsistent procedural actions resulted in reduced consumer loyalty and trust within positive brand relationships. Study 3 conceptually replicated both Study 1 and Study 2 by highlighting how procedural justice was initially discounted by consumers but was used to help maintain or adjust consumers’ relationship with a brand across many encounters with a positive CBR brand. Thus, the results of this dissertation have contributed and extended empirical knowledge within two separate areas of research while also providing evidence which accounted for previously unexpected changes in consumer behaviors and attitudes

Design of a Low Power 70MHz-110MHz Harmonic Rejection Filter with Class-AB Output Stage

An FM transmitter becomes the new feature in recent portable electronic development. A low power, integrable FM transmitter filter IC is required to meet the demand of FM transmitting feature. A low pass filter using harmonic rejection technique along with a low power class-AB output buffer is designed to meet the current market requirements on the FM transmitter chip. A harmonic rejection filter is designed to filter FM square wave signal from 70MHz to 110MHz into FM sine wave signal. Based on Fourier series, the harmonic rejection technique adds the phase shifted square waves to achieve better THD and less high frequency harmonics. The phase shifting is realized through a frequency divider, and the summation is implemented through a current summation circuit. A RC low pass filter with automatic tuning is designed to further attenuate unwanted harmonics. In this work, the filter's post layout simulation shows -53dB THD and harmonics above 800MHz attenuation of -99dB. The power consumption of the filter is less than 0.7mW. Output buffer stage is implemented through a resistor degenerated transconductor and a class-AB amplifier. Feedforward frequency compensation is applied to compensate the output class-AB stage, which extends the amplifier's operating bandwidth. A fully balanced class-AB driver is proposed to unleash the driving capability of common source output transistors. The output buffer reaches -43dB THD at 110MHz with 0.63Vpp output swing and drives 1mW into 50 load. The power consumption of the output buffer is 7.25mW. By using harmonic rejection technique, this work realizes the 70MHz-110MHz FM carrier filtering using TSMC 0.18um nominal process. Above 800MHz harmonics are attenuated to below -95dB. With 1.2V supply, the total power consumption including output buffer is 7.95mW. The total die area is 0.946mm2