ELECTROMECHANICAL INTERACTION ON THE DEFORMATION BEHAVIOR OF METALLIC MATERIALS

Metallic materials play important roles in providing electrical, thermal, and mechanical functions in electronic devices and systems. The understanding of the electrical-thermal-mechanical interaction caused by the passage of electric current with high density is important to improve the performance and reliability of electronic assembly and packaging. The electromechanical interaction on the deformation behavior of copper and tin is studied in this work. The electromechanical response of Cu strips was studied by passing a DC electric current. The electric resistance linearly increased with time before the occurrence of electric fusing. The electrothermal interaction led to the buckling of the Cu strips with the maximum deflection increasing with the increase of the electric current density. The total strain was found to be proportional to the square of the electric current density. A power law relation was used to describe the dependence of the time-to-fusing on the electric current density. Using the nanoindentation technique, the effect of electric current on the indentation deformation of copper and tin was studied. The reduced contact modulus of copper and tin decreased with increasing the electric current density. With the passage of a DC electric current, the indentation hardness of copper increased slightly with increasing electric current density. With the passage of an AC electric current, the indentation hardness of copper decreased with increasing the indentation deformation. With the passage of a DC electric current, the indentation hardness of tin decreased with increasing the indentation load, showing the normal indentation size effect. Both the limit of infinite depth and the characteristic length were dependent on the electric current density. Using the tensile creep technique, the creep deformation of pure tin was studied with the passage of a DC electric current. The steady state creep rate increased with the increase in temperature, tensile stress and electrical current density. For the same tensile stress and the same chamber temperature, the steady state creep rate increased linearly with the square of the electric current density. The electric current density has no significant effect on the stress exponent and activation energy of the tensile creep of tin for the experimental conditions

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices

Microstructure and processing effects on stress and reliability for through-silicon vias (TSVs) in 3D integrated circuits

Copper (Cu) Through-silicon via (TSV) is a key enabling element that provides the vertical connection between stacked dies in three-dimensional (3D) integration. The thermal expansion mismatch between Cu and Si induces complex stresses in and around the TSV structures, which can degrade the performance and reliability of 3DICs and are key concerns for technology development. In this dissertation, the effects of Cu microstructure and processing conditions on the stress characteristics and reliability of the TSV structure are studied. First, the stress characteristics of Cu TSV structures are investigated using the substrate curvature method. The substrate curvature measurement was supplemented by microstructure and finite element analyses (FEA) to investigate the mechanisms for the linear and nonlinear stress-temperature behaviors observed for the TSV structure. Implications of the near surface stress on carrier mobility change and device keep-out zone (KOZ) are discussed. Second, via extrusion, an important yield and reliability issue for 3D integration, is analyzed. Synchrotron x-ray microdiffraction technique was introduced for direct measurements of local stress and material behaviors in and around the TSV. Local plasticity near the top of the via was observed which provided direct experimental evidence to support the plasticity mechanism of via extrusion. An analytical model and FEA were used to analyze via extrusion based on local plasticity. Next, the effect of Cu microstructure effect on the thermomechanical behaviors of TSVs is investigated. The contribution from grain boundary and interfacial diffusion on via extrusion and the relaxation mechanisms are discussed. Potential approaches to minimize via extrusion are proposed. Finally, the stress characteristics of 3D die stack structures are studied using synchrotron x-ray microdiffraction. High resolution stress mappings were performed and verified by finite element analysis (FEA). FEA was further developed to estimate the stress effect on device mobility changes and the warpage of the integrated structure.Materials Science and Engineerin

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Body of Knowledge for Graphics Processing Units (GPUs)

Graphics Processing Units (GPU) have emerged as a proven technology that enables high performance computing and parallel processing in a small form factor. GPUs enhance the traditional computer paradigm by permitting acceleration of complex mathematics and providing the capability to perform weighted calculations, such as those in artificial intelligence systems. Despite the performance enhancements provided by this type of microprocessor, there exist tradeoffs in regards to reliability and radiation susceptibility, which may impact mission success. This report provides an insight into GPU architecture and its potential applications in space and other similar markets. It also discusses reliability, qualification, and radiation considerations for testing GPUs

On the nature and effect of power distribution noise in CMOS digital integrated circuits

The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,020,000 transistors, of which 510,000 are synchronously active. The circuit is configured as a linear array which, if fabricated using two-micron bulk CMOS technology, would be over eight centimetres long and three millimetres wide. In principle, the array will perform 1.5 x 10 to the power of 11 operations per second. 3. Power distribution noise associated with a non-array-based signal processor which, if fabricated in 2-micron bulk CMOS technology, would occupy 6.7 sq. cm. The circuit contains about 900,000 transistors, of which 600,000 are functional and about 300,000 are used for yield enhancement. The processor uses the RADIX-2 algorithm and is designed to achieve 2 x 10 to the power of 8 floating point operations per second. 4. The extent to which power distribution noise limits the level of integration and/ or performance of such circuits using standard and non-standard fabrication and packaging technology. 5. The extent to which the predicted power distribution noise levels affect circuit susceptibility to transient latch-up and electromigration. It concludes the nature of CMOS digital integrated circuit power distribution noise and recommends ways in which it may be minimised. It outlines an approach aimed at mechanising the developed simulation methodology so that the performance of power distribution networks may more routinely be assessed. Finally. it questions the long term suitability of mainly digital techniques for signal processing

A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches

High-temperature integrated circuit (IC) design is one of the new frontiers in microelectronics that can significantly improve the performance of the electrical systems in extreme environment applications, including automotive, aerospace, well-logging, geothermal, and nuclear. Power modules (DC-DC converters, inverters, etc.) are key components in these electrical systems. Power-to-volume and power-to-weight ratios of these modules can be significantly improved by employing silicon carbide (SiC) based power switches which are capable of operating at much higher temperature than silicon (Si) and gallium arsenide (GaAs) based conventional devices. For successful realization of such high-temperature power electronic circuits, associated control electronics also need to perform at high temperature. In any power converter, gate driver circuit performs as the interface between a low-power microcontroller and the semiconductor power switches. This dissertation presents design, implementation, and measurement results of a silicon-on-insulator (SOI) based high-temperature (\u3e200 _C) and high-voltage (\u3e30 V) universal gate driver integrated circuit with high drive current (\u3e3 A) for SiC power switches. This mixed signal IC has primarily been designed for automotive applications where the under-hood temperature can reach 200 _C. Prototype driver circuits have been designed and implemented in a Bipolar-CMOS- DMOS (BCD) on SOI process and have been successfully tested up to 200 _C ambient temperature driving SiC switches (MOSFET and JFET) without any heat sink and thermal management. This circuit can generate 30V peak-to-peak gate drive signal and can source and sink 3A peak drive current. Temperature compensating and temperature independent design techniques are employed to design the critical functional units like dead-time controller and level shifters in the driver circuit. Chip-level layout techniques are employed to enhance the reliability of the circuit at high temperature. High-temperature test boards have been developed to test the prototype ICs. An ultra low power on-chip temperature sensor circuit has also been designed and integrated into the gate-driver die to safeguard the driver circuit against excessive die temperature (_ 220 _C). This new temperature monitoring approach utilizes a reverse biased p-n junction diode as the temperature sensing element. Power consumption of this sensor circuit is less than 10 uW at 200 _C