An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems

This paper proposes a novel architecture for the generation of a programmable voltage reference: the background- calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time DT of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output ◦range [0.42 - 2.52] V, over the temperature range [-20 , 85] C. The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems

Model Building and Security Analysis of PUF-Based Authentication

In the context of hardware systems, authentication refers to the process of confirming the identity and authenticity of chip, board and system components such as RFID tags, smart cards and remote sensors. The ability of physical unclonable functions (PUF) to provide bitstrings unique to each component can be leveraged as an authentication mechanism to detect tamper, impersonation and substitution of such components. However, authentication requires a strong PUF, i.e., one capable of producing a large, unique set of bits per device, and, unlike secret key generation for encryption, has additional challenges that relate to machine learning attacks, protocol attacks and constraints on device resources. We describe the requirements for PUF-based authentication, and present a PUF primitive and protocol designed for authentication in resource constrained devices. Our experimental results are derived from a 28 nm Xilinx FPGA. In the authentication scenario, strong PUFs are required since the adversary could collect a subset of challenges and response pairsto build a model and predict the responses for unseen challenges. Therefore, strong PUFs need to provide exponentially large challenge space and be resilient to model building attacks. We investigate the security properties of a Hardware-embedded Delay PUF called HELP which leverages within-die variations in path delays within a hardware-implemented macro (functional unit) as the entropy source. Several features of the HELP processing engine significantly improve its resistance to model-building attacks. We also investigate a novel technique that significantly improves the statistically quality of the generated bitstring for HELP. Stability across environmental variations such as temperature and voltage, is critically important for Physically Unclonable Functions (PUFs). Nearly all existing PUF systems to date need a mechanism to deal with “bit flips” when exact regeneration of the bitstring is required, e.g., for cryptographic applications. Error correction (ECC) and error avoidance schemes have been proposed but both of these require helper data to be stored for the regeneration process. Unfortunately, helper data adds time and area overhead to the PUF system and provides opportunities for adversaries to reverse engineer the secret bitstring. We propose a non-volatile memory-based (NVM) PUF that is able to avoid bit flips without requiring any type of helper data. We describe the technique in the context of emerging nano-devices, in particular, resistive random access memory (Memristor) cells, but the methodology is applicable to any type of NVM including Flash

Novel Transistor Resistance Variation-based Physical Unclonable Functions with On-Chip Voltage-to-Digital Converter Designed for Use in Cryptographic and Authentication Applications

Security mechanisms such as encryption, authentication, and feature activation depend on the integrity of embedded secret keys. Currently, this keying material is stored as digital bitstrings in non-volatile memory on FPGAs and ASICs. However, secrets stored this way are not secure against a determined adversary, who can use specialized probing attacks to uncover the secret. Furthermore, storing these pre-determined bitstrings suffers from the disadvantage of not being able to generate the key only when needed. Physical Unclonable Functions (PUFs) have emerged as a superior alternative to this. A PUF is an embedded Integrated Circuit (IC) structure that is designed to leverage random variations in physical parameters of on-chip components as the source of entropy for generating random and unique bitstrings. PUFs also incorporate an on-chip infrastructure for measuring and digitizing these variations in order to produce bitstrings. Additionally, PUFs are designed to reproduce a bitstring on-demand and therefore eliminate the need for on-chip storage. In this work, two novel PUFs are presented that leverage the random variations observed in the resistance of transistors. A thorough analysis of the randomness, uniqueness and stability characteristics of the bitstrings generated by these PUFs is presented. All results shown are based on an exhaustive testing of a set of 63 chips designed with numerous copies of the PUFs on each chip and fabricated in a 90nm nine-metal layer technology. An on-chip voltage-to-digital conversion technique is also presented and tested on the set of 63 chips. Statistical results of the bitstrings generated by the on-chip digitization technique are compared with that of the voltage-derived bitstrings to evaluate the efficacy of the digitization technique. One of the most important quality metrics of the PUF and the on-chip voltage-to-digital converter, the stability, is evaluated through a lengthy temperature-voltage testing over the range of -40C to +85C and voltage variations of +/- 10% of the nominal supply voltage. The stability of both the bitstrings and the underlying physical parameters is evaluated for the PUFs using the data collected from the hardware experiments and supported with software simulations conducted on the devices. Several novel techniques are proposed and successfully tested that address known issues related to instability of PUFs to changing temperature and voltage conditions, thus rendering our PUFs more resilient to these changing conditions faced in practical use. Lastly, an analysis of the stability to changing temperature and voltage variations of a third PUF that leverages random variations in the resistance of the metal wires in the power and ground grids of a chip is also presented

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

CMOS Data Converters for Closed-Loop mmWave Transmitters

With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

Low-voltage data converters

With the growing demand for portable/consumer electronics, such as digital audio/video (AV), the downscaling of device dimensions, which enables the integration of an increasing number of transistors in a single chip, is mandatory. This trend also continuously pushes the power supply voltage down to reduce the power consumption and improve the reliability of gate dielectrics. While the reduction of power supply voltage is of great benefit to the essential digital blocks in the system like data storage and digital signal processing, it makes it hard to operate the important and indispensable analog building blocks such as data converters and drivers. In this thesis, the novel structures for the low-voltage digital-to-analog converter (DAC) and analog-to-digital converter (ADC) are presented. The research contributions of this work include (1) a sub-1V audio [delta sigma] DAC with one opamp used per channel to implement D/A conversion, 1st-order FIR and 2ndorder IIR filtering, as well as power amplification for the headphone, (2) a sub-1V pipelined ADC with the novel MDAC based on a low-voltage track-and-hold amplifier. Two prototypes, one is a 0.8V, 88dB dual-channel audio [delta sigma] DAC with headphone driver, the other one is a 0.8V, 10-bit, 10MS/s pipelined ADC were fabricated to verify the functionality of the proposed structures in standard CMOS processes

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.MIT Barker Engineering Library copy: printed in pages.Also issued printed in pages.Includes bibliographical references (leaves 179-184).CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally used in switched capacitor circuits. This research involves two complementary methods for addressing scaling issues. First is the development of two blind digital calibration techniques. Decision Boundary Gap Estimation (DBGE) removes static non-linearities and Chopper Offset Estimation (COE) nulls offsets in pipelined ADCs. Second is the development of circuits for a new architecture called zero-crossing based circuits (ZCBC) that is more amenable to scaling trends. To demonstrate these circuits and algorithms, two different ADCs were designed: an 8 bit, 200MS/s in TSMC 180nm technology, and a 12 bit, 50 MS/s in IBM 90nm technology. Together these techniques can be enabling technologies for both pipelined ADCs and general mixed signal design in deep sub-micron technologies.by Lane Gearle Brooks.Ph.D

Multi-wavelength infrared imaging computer systems and applications

This dissertation presents the development of three computer systems for multi-wavelength thermal imaging. Two computer systems were developed for the multi-wavelength imaging pyrometers (M-WIPs) that yield non-contact temperature measurements by remotely sensing the surface of objects with unknown wavelength-dependent emissivity. These M-WIP computer systems represent the state-of-art development in remote temperature measurement system based on the multi-wavelength approach. The dissertation research includes M-WIP computer system integration, software development, performance evaluation, and also applications in monitoring and control of temperature distribution of silicon wafers in a rapid thermal process system. The two M-WIPs are capable of data acquisition, signal processing, system calibration, radiometric measurement, parallel processing and process control. Temperature measurement experiments demonstrated the accuracy of ±1°C against blackbody and ±4°C for colorbody objects. Various algorithms were developed and implemented, including real-time two-point non-uniformity correction, thermal image pseudocoloring, PC to SUN workstation data transfer, automatic IR camera integration time control, and radiometric measurement parallel processing. A third computer system was developed for the demonstration of a 3-color InGaAs FPA which can provide images with information in three different IR wavelength range simultaneously. Numbers of functions were developed to demonstrate and characterize 3-color FPAs, and the system was delivered to be used by the 3-color FPA manufacturer

Negative Bias Temperature Instability (NBTI) Monitoring and Mitigation Technique for MOSFET

修士論

Reliability in the face of variability in nanometer embedded memories

In this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, as a first step, we propose a novel modeling methodology that helps evaluate the impact of circuit-level optimizations on architecture-level design choices. Choices made at the design-stage ensure conflicting requirements from higher-levels are decoupled. We then complement such design-time optimizations with a runtime mechanism that takes advantage of adaptive body-biasing to lower power whilst improving performance in the presence of variability. Our proposal uses a novel fully-digital variation tracking hardware using embedded DRAM (eDRAM) cells to monitor run-time changes in cache latency and leakage. A special fine-grain body-bias generator uses the measurements to generate an optimal body-bias that is needed to meet the required yield targets. A novel variation-tolerant and soft-error hardened eDRAM cell is also proposed as an alternate candidate for replacing existing SRAM-based designs in latency critical memory structures. In the ultra low-power domain where reliable operation is limited by the minimum voltage of operation (Vddmin), we analyse the impact of failures on cache functional margin and functional yield. Towards this end, we have developed a fully automated tool (INFORMER) capable of estimating memory-wide metrics such as power, performance and yield accurately and rapidly. Using the developed tool, we then evaluate the #effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Having a holistic perspective of memory-wide metrics helps us arrive at design-choices optimized simultaneously for multiple metrics needed for maintaining lifetime requirements