FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns

Output-capacitorless segmented low-dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.Peer ReviewedPostprint (author's final draft

An external capacitor-less low-dropout voltage regulator using a transconductance amplifier

This paper presents an external capacitor-less NMOS low-dropout (LDO) voltage regulator integrated with a standard CSMC 0.6 μm BiCMOS technology. Over a -55 ∘C to +125 ∘C temperature range, the fabricated LDO provides a stable and considerable amount of 3 A output current over wide ranges of output capacitance COUT (from zero to hundreds of μF ) and effective-series-resistance (ESR) (from tens of milliohms to several ohms). A low dropout voltage of 200 mV has been realised by accurate modelling. Operating with an input voltage ranging from 2.2 V to 5.5 V provides a scalable output voltage from 0.8 V to 3.6 V. When the load current jumps from 100 mA to 3 A within 3 μs, the output voltage overshoot remains as low as 50 mV without output capacitance, COUT. The system bandwidth is about 2 MHz, and hardly changes with load altering to ensure system stability. To improve the load transient response and driving capacity of the NMOS power transistor, a buffer with high input impedance and low output impedance is applied between the transconductance amplifier and the NMOS power transistor. The total area of fabricated LDO voltage regulator chip including pads is 2.1 mm×2.2 mm

3중 샘플링 방식 델타-시그마 ADC를 이용한 디지털 Capacitive MEMS 마이크로폰

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 김수환.본 논문에서는 트리플 샘플링 적분기를 사용한 Capacitive 방식의 MEMS 마이크로폰이 제시되었다. 트리플 샘플링은 델타-시그마 방식의 아날로그-디지털 변환기의 첫 번째 적분기에 사용되었고 크게 두 가지의 동작으로 구분된다. 첫 번째로 적분기의 입력에서 반주기 지연 차동 입력을 빼서 신호 크기를 2배로 만들는 방식. 두 번째로 DAC의 피드백 커패시터를 샘플링 커패시터로 사용하여 입력 전압을 추가로 증가시키는 방식이다. 추가적으로 기존에서 샘플링 커패시터를 증가시켜 신호의 크기를 증폭시키는 방식과 결합하여 실수배의 이득을 얻을 수 있다. 또한 추가적인 커패시터, 타이밍, 전류 소모 없이 구조 변경만으로 이를 달성하였기 때문에 별다른 trade-off 없이 신호의 크기를 증폭시킬 수 있었다. 추가적으로 트리플 샘플링 방식의 적분기 신호 전달 함수 및 잡음 분석 또한 포함하였다. 우리의 readout 회로는 공급 전압이 1.8V인 0.18 m CMOS 공정으로 구현하였고 single-ended capacitive MEMS 트랜스듀서를 사용하여 측정하였다. 전류 소모량은 520 μA 이다. 마이크로폰은 A-weighted 신호 대 잡음 비는 62.1 dBA, 음향 과부하 지점은 115 dB SPL을 달성하였고 칩의 die size는 0.98〖"mm" 〗^2 이다.A triple-sampling ΔΣ ADC can replace the programmable-gain amplifier commonly used in the readout circuit for a digital capacitive MEMS microphone. The input voltage can then be multiplied by subtracting a further half-period delayed differential input and using the feedback capacitor of the DAC as a sampling capacitor. This triple-sampling technique results in a readout circuit with sensitivity and noise performance comparable to recent designs, but with a reduced power requirement. CMRR improvement is achieved by subtracting differential inputs and superior noise performance compare to conventional structure, as amplifier noise and DAC kT/C noise is not amplified by triple-sampling structure while the signal is increased by its gain. Triple-sampling also can be operated as a single-to-differential circuit. A MEMS microphone incorporating this readout circuit, fabricated in a 0.18μm CMOS process, achieved an A-weighted SNR of 62.1 dBA at 94 dB SPL with 520 μA current consumption, to which triple-sampling was shown to contribute 4.5 dBA.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.1.1 MEMS MICROPHONE TRENDS 1 1.1.2 TYPE OF MEMS MICROPHONES 4 1.1.3 PREVIOUS WORKS 7 1.2 MEMS MICROPHONE BASIC TERMS 9 1.3 THESIS ORGANIZATION 12 CHAPTER 2 SYSTEM OVERVIEW 13 2.1 SYSTEM ARCHITECTURE 13 CHAPTER 3 INTERFACE CIRCUITS AND POWER MANAGEMENT CIRCUITS 16 3.1 PSEUDO-DIFFERENTIAL SOURCE FOLLOWER 17 3.2 CHARGE PUMP 19 3.3 LOW DROPOUT REGULATOR 22 3.3.1 DESIGN CONSIDERATION OF LOW DROPOUT REGULATOR 22 3.3.2 IMPLEMENTATION OF LOW DROPOUT REGULATOR 26 CHAPTER 4 TRIPLE-SAMPLING DELTA-SIGMA ADC 31 4.1 BASIC OF DELTA-SIGMA ADC 31 4.2 IMPLEMENTATION OF TRIPLE-SAMPLING DELTA-SIGMA MODULATOR 37 4.2.1 CONVENTIONAL 1ST INTEGRATOR STRUCTURE 37 4.2.2 CROSS-SAMPLING 1ST INTEGRATOR 40 4.2.3 TRIPLE-SAMPLING 1ST INTEGRATOR 43 4.2.4 STF ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 47 4.2.5 THERMAL NOISE ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 51 4.2 CIRCUIT IMPLEMENTATION OF DELTA-SIGMA ADC 57 CHAPTER 5 MEASUREMENT RESULTS 64 5.1 MEASUREMENT ENVIRONMENT 64 5.2 MEASUREMENT RESULTS 67 5.3 PERFORMANCE SUMMARY 72 CHAPTER 6 CONCLUSION 74 BIBLIOGRAPHY 76 한글초록 79박

Design of low-dropout regulator for ultra low power on-chip applications

Low Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture

A Case Study in CMOS Design Scaling for Analog Applications: The Ringamp LDO

As CMOS process nodes scale to smaller feature sizes, process optimizations are made to achieve improvements in digital circuit performance, such as increasing speed and memory, while decreasing power consumption. Unfortunately for analog design, these optimizations usually come at the expense of poorer transistor performance, such as reduced small signal output resistance and increased channel length modulation. The ring amplifier has been proposed as a digital solution to the analog scaling problem, by configuring digital inverters to function as analog amplifiers through deadzone biasing. As digital inverters naturally scale, the ring amplifier is a promising area of exploration for analog design. This work presents a ring amplifier scaling study by demonstration of scaling an output capacitor-less, ring amplifier based low-dropout voltage regulator designed in a standard 180 nm CMOS process down to a standard 90 nm CMOS process