Simplified Model Predictive Current Control for Surface- Mounted Permanent-Magnet Synchronous Motor Drives with Adaptive Duty Modulation

Parameter control and cost minimization are among the significant aspects of model predictive current controllers. However, with the conventional control scheme of fixed switching vector actuation, susceptibility to uncontrolled current ripples remains a primary concern. This paper presents a simplified approach of model predictive current controller baed on adaptive duty modulation for the surface-mounted permanent-magnet synchronous motor (SPMSM). In this method, the implementation of two successive synthesized voltage vectors adopts the adpative soft-switching combination in each control period. Experimental results validate performance improvement and optimize current predictive accuracy

Simplified Model Predictive Current Control for Surface- Mounted Permanent-Magnet Synchronous Motor Drives with Adaptive Duty Modulation

Parameter control and cost minimization are among the significant aspects of model predictive current controllers. However, with the conventional control scheme of fixed switching vector actuation, susceptibility to uncontrolled current ripples remains a primary concern. This paper presents a simplified approach of model predictive current controller baed on adaptive duty modulation for the surface-mounted permanent-magnet synchronous motor (SPMSM). In this method, the implementation of two successive synthesized voltage vectors adopts the adpative soft-switching combination in each control period. Experimental results validate performance improvement and optimize current predictive accuracy

EXPERIMENTAL ANALYSIS OF GATE DRIVE CONTROL SYSTEM FOR SYNCHRONOUS DC/DC CONVERTER

The design of the PCB board is important as it affects the overall performance of the overall system. The most common problem that affects the performance and efficiency of the PCB board are partitioning of the circuits, the problem of interconnecting traces, grounding schemes and thermal management. Overall, the primary objectives of the project are to understand the process flow of PCB and to acquire knowledge about PCB fabrication. Meanwhile, the secondary objectives of the project are to apply high frequency DC-DC Converter on PCB fabrication and lastly to test and verify the output of PCB fabrication. SRBC-PWM and SRBC-compensator-AGD are successfully implemented on PCB board. The knowledge about PCB design is acquired and the problems overcome while fabricating PCB are managed to overcome

Hybrid monolithic integration of high-power DC-DC converters in a high-voltage technology

The supply of electrical energy to home, commercial, and industrial users has become ubiquitous, and it is hard to imagine a world without the facilities provided by electrical energy. Despite the ever increasing efficiency of nearly every electrical application, the worldwide demand for electrical power continues to increase, since the number of users and applications more than compensates for these technological improvements. In order to maintain the affordability and feasibility of the total production, it is essential for the distribution of the produced electrical energy to be as efficient as possible. In other words the loss in the power distribution is to be minimized. By transporting electrical energy at the maximum safe voltage, the current in the conductors, and the associated conduction loss can remain as low as possible. In order to optimize the total efficiency, the high transportation voltage needs to be converted to the appropriate lower voltage as close as possible to the end user. Obviously, this conversion also needs to be as efficient, affordable, and compact as possible. Because of the ever increasing integration of electronic systems, where more and more functionality is combined in monolithically integrated circuits, the cost, the power consumption, and the size of these electronic systems can be greatly reduced. This thorough integration is not limited to the electronic systems that are the end users of the electrical energy, but can also be applied to the power conversion itself. In most modern applications, the voltage conversion is implemented as a switching DC-DC converter, in which electrical energy is temporarily stored in reactive elements, i.e. inductors or capacitors. High switching speeds are used to allow for a compact and efficient implementation. For low power levels, typically below 1 Watt, it is possible to monolithically implement the voltage conversion on an integrated circuit. In some cases, this is even done on the same integrated circuit that is the end user of the electrical energy to minimize the system dimensions. For higher power levels, it is no longer feasible to achieve the desired efficiency with monolithically integrated components, and some external components prove indispensable. Usually, the reactive components are the main limiting factor, and are the first components to be moved away from the integrated circuit for increasing power levels. The semiconductor components, including the power transistors, remain part of the integrated circuit. Using this hybrid approach, it is possible in modern converterapplications to process around 60 Watt, albeit limited to voltages of a few Volt. For hybrid integrated converters with an output voltage of tens of Volt, the power is limited to approximately 10 Watt. For even higher power levels, the integrated power transistors also become a limiting factor, and are replaced with discrete power devices. In these discrete converters, greatly increased power levels become possible, although the system size rapidly increases. In this work, the limits of the hybrid approach are explored when using so-called smart-power technologies. Smart-power technologies are standard lowcost submicron CMOS technologies that are complemented with a number of integrated high-voltage devices. By using an appropriate combination of smart-power technologies and circuit topologies, it is possible to improve on the current state-of-the-art converters, by optimizing the size, the cost, and the efficiency. To determine the limits of smart-power DC-DC converters, we first discuss the major contributing factors for an efficient energy distribution, and take a look at the role of voltage conversion in the energy distribution. Considering the limitations of the technologies and the potential application areas, we define two test-cases in the telecommunications sector for which we want to optimize the hybrid monolithic integration in a smart-power technology. Subsequently, we explore the specifications of an ideal converter, and the relevant properties of the affordable smart-power technologies for the implementation of DC-DC converters. Taking into account the limitations of these technologies, we define a cost function that allows to systematically evaluate the different potential converter topologies, without having to perform a full design cycle for each topology. From this cost function, we notice that the de facto default topology selection in discrete converters, which is typically based on output power, is not optimal for converters with integrated power transistors. Based on the cost function and the boundary conditions of our test-cases, we determine the optimal topology for a smart-power implementation of these applications. Then, we take another step towards the real world and evaluate the influence of parasitic elements in a smart-power implementation of switching converters. It is noticed that the voltage overshoot caused by the transformer secondary side leakage inductance is a major roadblock for an efficient implementation. Since the usual approach to this voltage overshoot in discrete converters is not applicable in smart-power converters due to technological limitations, an alternative approach is shown and implemented. The energy from the voltage overshoot is absorbed and transferred to the output of the converter. This allows for a significant reduction in the voltage overshoot, while maintaining a high efficiency, leading to an efficient, compact, and low-cost implementation. The effectiveness of this approach was tested and demonstrated in both a version using a commercially available integrated circuit, and our own implementation in a smart-power integrated circuit. Finally, we also take a look at the optimization of switching converters over the load range by exploiting the capabilities of highly integrated converters. Although the maximum output power remains one of the defining characteristics of converters, it has been shown that most converters spend a majority of their lifetime delivering significantly lower output power. Therefore, it is also desirable to optimize the efficiency of the converter at reduced output current and output power. By splitting the power transistors in multiple independent segments, which are turned on or off in function of the current, the efficiency at low currents can be significantly improved, without introducing undesirable frequency components in the output voltage, and without harming the efficiency at higher currents. These properties allow a near universal application of the optimization technique in hybrid monolithic DC-DC converter applications, without significant impact on the complexity and the cost of the system. This approach for the optimization of switching converters over the load range was demonstrated using a boost converter with discrete power transistors. The demonstration of our smart-power implementation was limited to simulations due to an issue with a digital control block. On a finishing note, we formulate the general conclusions and provide an outlook on potential future work based on this research

Development of Maximum Power Extraction Algorithms for PV system With Non-Uniform Solar Irradiances

This thesis addresses the problem of extraction of maximum power from PV arrays subjected to non-uniform solar irradiances e.g partial shading. In the past, a number of maximum power point tracking algorithms (MPPTs) such as Perturb & Observe, Hill climbing, Incremental Conductance, etc. have been proposed. These are extensively used for obtaining maximum power from a PV module to maximize power yield from PV systems under uniform solar irradiance. However, these techniques have not considered partial shading conditions and the stochastic nature of solar insolation. In the event of non-uniform solar insolation, a number multiple maximum power points (MPPs) appear in the power-voltage characteristic of the PV module. In the present thesis, the stochastic nature of the solar insolation is considered to obtain the global MPP of a PV module with a focus on developing global optimization techniques for MPPT that would handle the multiple MPPs. Thus, the thesis will address the above problem by developing a number of global MPPT algorithms. In this thesis, an extensive review on MPPT algorithms for both uniform and non-uniform insolation levels is presented. Subsequently, an analysis with respect to their merits, demerits and applications have been provided in order to design new MPPTs to achieve higher MPPT efficiency under non-uniform solar irradiances. Firstly, PV modules are modelled with and without bypass diodes for handling Partial shading conditions (PSCs). Then, a new Ring pattern (RP) configuration has been proposed which is compared with different existing configurations such as Series parallel (SP), Total cross tied(TCT) and Bridge linked(BL) configurations on the basis of maximum power and fill factor. As described earlier, under non-uniform irradiances the MPPT problem boil down to determining the global MPP. Thus, the MPPT problem can be cast as a global optimization problem. It may be noted that evolutionary computing approaches are extensively used for obtaining global optimum solutions. One of the most recent evolutionary optimization techniques called grey wolf optimization technique has gained enormous popularity as an efficient global optimization approach. In view of this, Grey wolf optimization is employed to design a global MPPT such that maximum power from PV modules can be extracted which will work under partial shading conditions. Its performance has been compared with two existing MPPTs namely P&O and IPSO based MPPT methods. From the obtained simulation and experimental results, it was found that the GWO based MPPT exhibits superior MPPT performance as compared to both P&O and IPSO MPPTs on the basis of dynamic response, faster convergence to GP and higher tracking efficiency. Further, in order to scale down the search space of GWO which helps to speed up for achieving convergence towards the GP, a fusion of GWO-MPPT with P&O MPPT for obtaining maximum power from a PV system with different possible patterns is developed. An experimental setup of 600W solar simulator is used in the laboratory having characteristics of generating partial shading situation. Firstly, the developed algorithms were implemented for a PV system using MATLAB/SIMULINK. Subsequently, the aforesaid experimental setup is used to implement the proposed global MPPT algorithms. From the obtained simulation and experimental results it is observed that the Hybrid-MPPT converges to the GP with least time enabling highest possible maximum power from the solar PV system. In this thesis, analytical modeling of PV modules for handling non-uniform irradiances is pursued as well as a new RP configuration of PV modules is developed to achieve maximum power and fill factor. In order to extract maximum power from PV panels subjected to non-uniform solar irradiances, two new MPPT algorithms are developed namely Grey wolf optimization based MPPT (GWO-MPPT) and GWO assisted PO (GWO-PO)

Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects