비디오 클럭 주파수 보상 구조를 이용한 디스플레이포트 수신단 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 정덕균.This thesis presents the design of DisplayPort receiver which is a high speed digital display interface replacing existing interfaces such as DVI, HDMI, LVDS and so on. The two prototype chips are fabricated, one is a 5.4/2.7/1.62-Gb/s multi-rate DisplayPort receiver and the other is a 2.7/1.62-Gb/s multi-rate Embedded DisplayPort (eDP) receiver for an intra-panel display interface. The first receiver which is designed to support the external box-to-box display connection provides up to 4K resolution (4096×2160) with the maximum data rate of 21.6 Gb/s when 4 lanes are all used. The second one aims to connect internal chip-to-chip connection such as graphic processors to display panels in notebooks or tablet PCs. It supports the maximum data rate of 10.8 Gb/s with 4-lane operation which is able to provide the resolution of WQXGA (2560×1600). Since there is no dedicated clock channel, it must contain clock and data recovery (CDR) circuit to extract the link clock from the data stream. All-Digital CDR (ADCDR) is adopted for area efficiency and better performances of the multi-rate operation. The link rate is fixed but the video clock frequency range is fairly wide for supporting all display resolutions and frame rates. Thus, the wide range video clock frequency synthesizer is essential for reconstructing the transmitted video data. A source device starts link training before transmitting video data to recover the clock and establish the link. When the loss of synchronization between the source device and the sink device happens, it usually restarts the link training and try to re-establish the link. Since link training spends several milliseconds for initializing, the video image is not displayed properly in the sink device during this interval. The proposed clock recovery scheme can significantly shorten the time to recover from the link failure with the ADCDR topology. Once the link is established after link training, the ADCDR memorizes the DCO codes of the synchronization state and when the loss of synchronization happens, it restores the previous DCO code so that the clock is quickly recovered from the failure state without the link re-training. The direct all-digital frequency synthesizer is proposed to generate the cycle-accurate video clock frequency. The video clock frequency has wide range to cover all display formats and is determined by the division ratio of large M and N values. The proposed frequency synthesizer using a programmable integer divider and a multi-phase switching fractional divider with the delta-sigma modulation exhibits better performances and reduces the design complexity operating with the existing clock from the ADCDR circuit. In asynchronous clock system, the transmitted M value which changes over time is measured by using a counter running with the long reference period (N cycles) and updated once per blank period. Thus, the transmitted M is not accurate due to its low update rate, transport latency and quantization error. The proposed frequency error compensation scheme resolves these problems by monitoring the status of FIFO between the clock domains. The first prototype chip is fabricated in a 65-nm CMOS process and the physical layer occupies 1.39 mm2 and the estimated area of the link layer is 2.26 mm2. The physical layer dissipates 86/101/116 mW at 1.62/2.7/5.4 Gb/s data rate with all 4-lane operation. The power consumption of the link layer is 107/145/167 mW at 1.62/2.7/5.4 Gb/s. The second prototype chip, fabricated in a 0.13μm CMOS process, presents the physical layer area of 1.59 mm2 and the link layer area of 3.01 mm2. The physical layer dissipates 21 mW at 1.62 Gb/s and 29 mW at 2.7 Gb/s with 2-lane operation. The power consumption of the link layer is 31 mW at 1.62 Gb/s and 41 mW at 2.7 Gb/s with 2-lane operation. The core area of the video clock synthesizer occupies 0.04 mm2 and the power dissipation is 5.5 mW at a low bit rate and 9.1 mW at a high bit rate. The output frequency range is 25 to 330 MHz.ABSTRACT I CONTENTS IV LIST OF FIGURES VII LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 MOTIVATION 4 1.3 THESIS ORGANIZATION 12 CHAPTER 2 DIGITAL DISPLAY INTERFACE 13 2.1 OVERVIEW 13 2.2 DISPLAYPORT INTERFACE CHARACTERISTICS 18 2.2.1 DISPLAYPORT VERSION 1.2 18 2.2.2 EMBEDDED DISPLAYPORT VERSION 1.2 21 2.3 DISPLAYPORT INTERFACE ARCHITECTURE 23 2.3.1 LAYERED ARCHITECTURE 23 2.3.2 MAIN STREAM PROTOCOL 27 2.3.3 INITIALIZATION AND LINK TRAINING 30 2.3.3 VIDEO STREAM CLOCK RECOVERY 35 CHAPTER 3 DESIGN OF DISPLAYPORT RECEIVER 39 3.1 OVERVIEW 39 3.2 PHYSICAL LAYER 43 3.3 LINK LAYER 55 3.3.1 OVERALL ARCHITECTURE 55 3.3.2 AUX CHANNEL 58 3.3.3 VIDEO TIMING GENERATION 61 3.3.4 CONTENT PROTECTION 63 3.3.5 AUDIO TRANSMISSION 66 3.4 EXPERIMENTAL RESULTS 68 CHAPTER 4 DESIGN OF EMBEDDED DISPLAYPORT RECEIVER 81 4.1 OVERVIEW 81 4.2 PHYSICAL LAYER 84 4.3 LINK LAYER 88 4.3.1 OVERALL ARCHITECTURE 88 4.3.2 MAIN LINK STREAM 90 4.3.3 CONTENT PROTECTION 93 4.4 PROPOSED CLOCK RECOVERY SCHEME 94 4.5 EXPERIMENTAL RESULTS 100 CHAPTER 5 PROPOSED VIDEO CLOCK SYNTHESIZER AND FREQUENCY CONTROL SCHEME 113 5.1 MOTIVATION 113 5.2 PROPOSED VIDEO CLOCK SYNTHESIZER 115 5.3 BUILDING BLOCKS 121 5.4 FREQUENCY ERROR COMPENSATION 126 5.5 EXPERIMENTAL RESULTS 131 CHAPTER 6 CONCLUSION 138 BIBLIOGRAPHY 141 초 록 152Docto

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities

Architecture for grid-enabled instrumentation in extreme environments

Technological progress in recent decades has led to sensor networks and robotic explorers becoming principal tools for investigation of remote or "hostile" environments where it is difficult, if not impossible for humans to intervene. These situations include deep ocean and space environments where the devices can be subject to extreme pressures, temperatures and radiation levels. It is a costly enterprise to deploy an instrument in such settings and therefore reliable operation and ease of use are requisite features to build into the basic fabric of the machine. This thesis describes the design and implementation of a modular machine system based on a peer-to-peer, decentralised network topology where the power supply and electronic hardware resources are distributed homogeneously throughout a network of nodes. Embedded within each node is a minimal, low-power single board computer on which a real-time operating system and MicroCANopen protocol stack are operating to realise a standard interface to the network. The network is based on a grid paradigm where nodes act as resource producers and consumers, sharing information so that the machine system as a whole can perform tasks. The resulting architecture supports "plug-and-play" flexibility, to allow users or system developers to reconfigure or expand its capabilities by adding/removing nodes at a later time. An immediate application of this instrument is in-situ sampling of microbes in extreme aqueous habitats. The microbial sampler is targeted at providing improved sampling capabilities when performing physical, chemical and biological investigations in deep- ocean hydrothermal vent environments. At these depths the instrument is subject to immense pressures of many thousand pounds per square inch, where superheated, corrosive, mineral-loaded vent fluids mix with near-freezing seawater. In the longer term, it is anticipated that this flexible, open interface architecture on which the microbial sampler instrument is based will be applicable more generally to other sectors, including commercial and scientific markets.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Field-Deployable Concurrent-Transmitter Networks for Long Term Environmental Monitoring

In this work, I draw upon my experience with field deployments of low-power data collection systems to come up with new approaches to long-term environmental monitoring (LTEM). Our goal is to develop long-lived, reliable systems that can be deployed by non-experts. The specific requirements of LTEM systems lead us to pursue techniques which can take advantage of the natural heirarchies that exist in sensor deployments while avoiding the difficulties inherent in selecting efficient data transmission routes in the face of unreliable hardware and difficult-to-measure link dynamics. The approach we advocate eschews traditional single-path routing and transmission methods in favor of approaches that leverage non-destructive simultaneous packet transmissions over subsets of the network. We apply this principle to develop a medium access protocol suitable for dense networks (Flip-MAC) as well as a method for identifying the set of potentially-useful forwarders between a data source and its destination (CX). This document not only characterizes and evaluates the low-level behavior of these protocols, but also describes the design of a larger multi-tiered data collection system based on CX, a suite of hardware which is well-suited to both CX and common deployment patterns, and the design of a ``dirt-to-database'' system which gives domain scientists the tools they need to deploy and manage networks on their own

Architecture for grid-enabled instrumentation in extreme environments

Technological progress in recent decades has led to sensor networks and robotic explorers becoming principal tools for investigation of remote or "hostile" environments where it is difficult, if not impossible for humans to intervene. These situations include deep ocean and space environments where the devices can be subject to extreme pressures, temperatures and radiation levels. It is a costly enterprise to deploy an instrument in such settings and therefore reliable operation and ease of use are requisite features to build into the basic fabric of the machine. This thesis describes the design and implementation of a modular machine system based on a peer-to-peer, decentralised network topology where the power supply and electronic hardware resources are distributed homogeneously throughout a network of nodes. Embedded within each node is a minimal, low-power single board computer on which a real-time operating system and MicroCANopen protocol stack are operating to realise a standard interface to the network. The network is based on a grid paradigm where nodes act as resource producers and consumers, sharing information so that the machine system as a whole can perform tasks. The resulting architecture supports "plug-and-play" flexibility, to allow users or system developers to reconfigure or expand its capabilities by adding/removing nodes at a later time. An immediate application of this instrument is in-situ sampling of microbes in extreme aqueous habitats. The microbial sampler is targeted at providing improved sampling capabilities when performing physical, chemical and biological investigations in deep- ocean hydrothermal vent environments. At these depths the instrument is subject to immense pressures of many thousand pounds per square inch, where superheated, corrosive, mineral-loaded vent fluids mix with near-freezing seawater. In the longer term, it is anticipated that this flexible, open interface architecture on which the microbial sampler instrument is based will be applicable more generally to other sectors, including commercial and scientific markets

Research and technology

Significant research and technology activities at the Johnson Space Center (JSC) during Fiscal Year 1990 are reviewed. Research in human factors engineering, the Space Shuttle, the Space Station Freedom, space exploration and related topics are covered

Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un

Range Information Systems Management (RISM) Phase 1 Report

RISM investigated alternative approaches, technologies, and communication network architectures to facilitate building the Spaceports and Ranges of the future. RISM started by document most existing US ranges and their capabilities. In parallel, RISM obtained inputs from the following: 1) NASA and NASA-contractor engineers and managers, and; 2) Aerospace leaders from Government, Academia, and Industry, participating through the Space Based Range Distributed System Working Group (SBRDSWG), many of whom are also; 3) Members of the Advanced Range Technology Working Group (ARTWG) subgroups, and; 4) Members of the Advanced Spaceport Technology Working Group (ASTWG). These diverse inputs helped to envision advanced technologies for implementing future Ranges and Range systems that builds on today s cabled and wireless legacy infrastructures while seamlessly integrating both today s emerging and tomorrow s building-block communication techniques. The fundamental key is to envision a transition to a Space Based Range Distributed Subsystem. The enabling concept is to identify the specific needs of Range users that can be solved through applying emerging communication tec