A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS

An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a high-speed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-μm standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with up to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results

Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

Digital Signal Processing Techniques Applied to Radio over Fiber Systems

The dissertation aims to analyze different Radio over Fiber systems for the front-haul applications. Particularly, analog radio over fiber (A-RoF) are simplest and suffer from nonlinearities, therefore, mitigating such nonlinearities through digital predistortion are studied. In particular for the long haul A-RoF links, direct digital predistortion technique (DPDT) is proposed which can be applied to reduce the impairments of A-RoF systems due to the combined effects of frequency chirp of the laser source and chromatic dispersion of the optical channel. Then, indirect learning architecture (ILA) based structures namely memory polynomial (MP), generalized memory polynomial (GMP) and decomposed vector rotation (DVR) models are employed to perform adaptive digital predistortion with low complexities. Distributed feedback (DFB) laser and vertical capacity surface emitting lasers (VCSELs) in combination with single mode/multi-mode fibers have been linearized with different quadrature amplitude modulation (QAM) formats for single and multichannel cases. Finally, a feedback adaptive DPD compensation is proposed. Then, there is still a possibility to exploit the other realizations of RoF namely digital radio over fiber (D-RoF) system where signal is digitized and transmits the digitized bit streams via digital optical communication links. The proposed solution is robust and immune to nonlinearities up-to 70 km of link length. Lastly, in light of disadvantages coming from A-RoF and D-RoF, it is still possible to take only the advantages from both methods and implement a more recent form knows as Sigma Delta Radio over Fiber (S-DRoF) system. Second Order Sigma Delta Modulator and Multi-stAge-noise-SHaping (MASH) based Sigma Delta Modulator are proposed. The workbench has been evaluated for 20 MHz LTE signal with 256 QAM modulation. Finally, The 6x2 GSa/s sigma delta modulators are realized on FPGA to show a real time demonstration of S-DRoF system. The demonstration shows that S-DRoF is a competitive competitor for 5G sub-6GHz band applications

Integrated Transversal Equalizers in High-Speed Fiber-Optic Systems

Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-µm SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-µm multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10^-5 to less than 10^-12

The Development of Unique Focal Planes for High-Resolution Suborbital and Ground-Based Exploration

abstract: The development of new Ultra-Violet/Visible/IR range (UV/Vis/IR) astronomical instrumentation that use novel approaches for imaging and increase the accessibility of observing time for more research groups is essential for rapid innovation within the community. Unique focal planes that are rapid-prototyped, low cost, and provide high resolution are key. In this dissertation the emergent designs of three unique focal planes are discussed. These focal planes were each designed for a different astronomical platform: suborbital balloon, suborbital rocket, and ground-based observatory. The balloon-based payload is a hexapod-actuated focal plane that uses tip-tilt motion to increase angular resolution through the removal of jitter – known as the HExapod Resolution-Enhancement SYstem (HERESY), the suborbital rocket imaging payload is a Jet Propulsion Laboratory (JPL) delta-doped charge-coupled device (CCD) packaged to survive the rigors of launch and image far-ultra-violet (FUV) spectra, and the ground-based observatory payload is a star centroid tracking modification to the balloon version of HERESY for the tip-tilt correction of atmospheric turbulence. The design, construction, verification, and validation of each focal plane payload is discussed in detail. For HERESY’s balloon implementation, pointing error data from the Stratospheric Terahertz Observatory (STO) Antarctic balloon mission was used to form an experimental lab test setup to demonstrate the hexapod can eliminate jitter in flight-like conditions. For the suborbital rocket focal plane, a harsh set of unit-level tests to ensure the payload could survive launch and space conditions, as well as the characterization and optimization of the JPL detector, are detailed. Finally, a modification of co-mounting a fast-read detector to the HERESY focal plane, for use on ground-based observatories, intended to reduce atmospherically induced tip-tilt error through the centroid tracking of bright natural guidestars, is described.Dissertation/ThesisDoctoral Dissertation Exploration Systems Design 201

Congestion Control for Network-Aware Telehaptic Communication

Telehaptic applications involve delay-sensitive multimedia communication between remote locations with distinct Quality of Service (QoS) requirements for different media components. These QoS constraints pose a variety of challenges, especially when the communication occurs over a shared network, with unknown and time-varying cross-traffic. In this work, we propose a transport layer congestion control protocol for telehaptic applications operating over shared networks, termed as dynamic packetization module (DPM). DPM is a lossless, network-aware protocol which tunes the telehaptic packetization rate based on the level of congestion in the network. To monitor the network congestion, we devise a novel network feedback module, which communicates the end-to-end delays encountered by the telehaptic packets to the respective transmitters with negligible overhead. Via extensive simulations, we show that DPM meets the QoS requirements of telehaptic applications over a wide range of network cross-traffic conditions. We also report qualitative results of a real-time telepottery experiment with several human subjects, which reveal that DPM preserves the quality of telehaptic activity even under heavily congested network scenarios. Finally, we compare the performance of DPM with several previously proposed telehaptic communication protocols and demonstrate that DPM outperforms these protocols.Comment: 25 pages, 19 figure

Effect and Compensation of Timing Jitter in Through-Wall Human Indication via Impulse Through-Wall Radar

Impulse through-wall radar (TWR) is considered as one of preferred choices for through-wall human indication due to its good penetration and high range resolution. Large bandwidth available for impulse TWR results in high range resolution, but also brings an atypical adversity issue not substantial in narrowband radars — high timing jitter effect, caused by the non-ideal sampling clock at the receiver. The fact that impulse TWR employs very narrow pulses makes little jitter inaccuracy large enough to destroy the signal correlation property and then degrade clutter suppression performance. In this paper, we focus on the timing jitter impact on clutter suppression in through-wall human indication via impulse TWR. We setup a simple timing jitter model and propose a criterion namely average range profile (ARP) contrast is to evaluate the jitter level. To combat timing jitter, we also develop an effective compensation method based on local ARP contrast maximization. The proposed method can be implemented pulse by pulse followed by exponential average background subtraction algorithm to mitigate clutters. Through-wall experiments demonstrate that the proposed method can dramatically improve through-wall human indication performance