3,769 research outputs found

    Channel Characterization for Chip-scale Wireless Communications within Computing Packages

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    Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 201

    On the design of an Ohmic RF MEMS switch for reconfigurable microstrip antenna applications

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    This paper presents the analysis, design and simulation of a direct contact (dc) RF MEMS switch specified for reconfigurable microstrip array antennas. The proposed switch is indented to be built on PCB via a monolithic technology together with the antenna patches. The proposed switch will be used to allow antenna beamforming in the operating frequency range between 2GHz and 4GHz. This application requires a great number of these switches to be integrated with an array of microstrip patch elements. The proposed switch fulfills the switching characteristics as concerns the five requirements (loss, linearity, voltage/power handling, small size/power consumption, temperature), following a relatively simple design, which ensures reliability, robustness and high fabrication yiel

    Plasmonic Antennas Hybridized with Dielectric Waveguides

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    For the purpose of using plasmonics in an integrated scheme where single emitters can be probed efficiently, we experimentally and theoretically study the scattering properties of single nano-rod gold antennas as well as antenna arrays placed on one-dimensional dielectric silicon nitride waveguides. Using real space and Fourier microscopy correlated with waveguide transmission measurements, we quantify the spectral properties, absolute strength and directivity of scattering. The scattering processes can be well understood in the framework of the physics of dipolar objects placed on a planar layered environment with a waveguiding layer. We use the single plasmonic structures on top of the waveguide as dipolar building blocks for new types of antennas where the waveguide enhances the coupling between antenna elements. We report on waveguide hybridized Yagi-Uda antennas which show directionality in out-coupling of guided modes as well as directionality for in-coupling into the waveguide of localized excitations positioned at the feed element. These measurements together with simulations demonstrate that this system is ideal as a platform for plasmon quantum optics schemes as well as for fluorescence lab-on-chip applications

    Channel characterization for chip-scale wireless communications within computing packages

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    Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Peer ReviewedPostprint (author's final draft
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