31,916 research outputs found
Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency
Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation presents the design and analysis of a real-time adaptive DVS architecture for paralleled Multi-Threshold NULL Convention Logic (MTNCL) systems. Results show that energy-efficient systems with low area overhead can be created using this approach
Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction
Recent research has shown that combining dynamic voltage scaling (DVS) and adaptive body bias (ABB) techniques achieve the highest reduction in embedded systems energy dissipation [1]. In this paper we show that it is possible to produce comparable energy saving to that obtained using combined DVS and ABB techniques but with reduced hardware cost achieved by employing processing elements (PEs) with separate DVS or ABB capability. A co-synthesis methodology which is aware of tasks’ power-composition profile (the ratio of the dynamic power to the leakage power) is presented. The methodology selects voltage scaling capabilities (DVS, ABB, or combined DVS and ABB) for the PEs, maps, schedules, and voltage scales applications given as task graphs with timing constraints, aiming to dynamic and leakage energy reduction at low hardware cost. We conduct detailed experiments, including a real-life example, to demonstrate the effectiveness of our methodology. We demonstrate that it is possible to produce designs that contain PEs with only DVS or ABB technique but have energy dissipation that are only 4.4% higher when compared with the same designs that employ PEs with combined DVS and ABB capabilities
A survey of dynamic power optimization techniques
One of the most important considerations for the current VLSI/SOC design is power, which can be classified into power analysis and optimization. In this survey, the main concepts of power optimization including the sources and policies are introduced. Among the various approaches, dynamic power management (DPM), which implies to change devices states when they are not working at the highest speed or at their full capacity, is the most efficient one. Our explanations accompanying the figures specify the abstract concepts of DPM. This paper briefly surveys both heuristic and stochastic policies and discusses their advantages and disadvantages
A software controlled voltage tuning system using multi-purpose ring oscillators
This paper presents a novel software driven voltage tuning method that
utilises multi-purpose Ring Oscillators (ROs) to provide process variation and
environment sensitive energy reductions. The proposed technique enables voltage
tuning based on the observed frequency of the ROs, taken as a representation of
the device speed and used to estimate a safe minimum operating voltage at a
given core frequency. A conservative linear relationship between RO frequency
and silicon speed is used to approximate the critical path of the processor.
Using a multi-purpose RO not specifically implemented for critical path
characterisation is a unique approach to voltage tuning. The parameters
governing the relationship between RO and silicon speed are obtained through
the testing of a sample of processors from different wafer regions. These
parameters can then be used on all devices of that model. The tuning method and
software control framework is demonstrated on a sample of XMOS XS1-U8A-64
embedded microprocessors, yielding a dynamic power saving of up to 25% with no
performance reduction and no negative impact on the real-time constraints of
the embedded software running on the processor
Scaling Configuration of Energy Harvesting Sensors with Reinforcement Learning
With the advent of the Internet of Things (IoT), an increasing number of
energy harvesting methods are being used to supplement or supplant battery
based sensors. Energy harvesting sensors need to be configured according to the
application, hardware, and environmental conditions to maximize their
usefulness. As of today, the configuration of sensors is either manual or
heuristics based, requiring valuable domain expertise. Reinforcement learning
(RL) is a promising approach to automate configuration and efficiently scale
IoT deployments, but it is not yet adopted in practice. We propose solutions to
bridge this gap: reduce the training phase of RL so that nodes are operational
within a short time after deployment and reduce the computational requirements
to scale to large deployments. We focus on configuration of the sampling rate
of indoor solar panel based energy harvesting sensors. We created a simulator
based on 3 months of data collected from 5 sensor nodes subject to different
lighting conditions. Our simulation results show that RL can effectively learn
energy availability patterns and configure the sampling rate of the sensor
nodes to maximize the sensing data while ensuring that energy storage is not
depleted. The nodes can be operational within the first day by using our
methods. We show that it is possible to reduce the number of RL policies by
using a single policy for nodes that share similar lighting conditions.Comment: 7 pages, 5 figure
Adaptive transient solution of nonuniform multiconductor transmission lines using wavelets
Abstract—This paper presents a highly adaptive algorithm for the transient simulation of nonuniform interconnects loaded with arbitrary nonlinear and dynamic terminations. The discretization of the governing equations is obtained through a weak formula-tion using biorthogonal wavelet bases as trial and test functions. It is shown how the multiresolution properties of wavelets lead to very sparse approximations of the voltages and currents in typical transient analyzes. A simple yet effective time–space adaptive al-gorithm capable of selecting the minimal number of unknowns at each time iteration is described. Numerical results show the high degree of adaptivity of the proposed scheme. Index Terms—Electromagnetic (EM) transient analysis, multi-conductor transmission lines (TLs), wavelet transforms. I
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
Recent technological advances have greatly improved the performance and
features of embedded systems. With the number of just mobile devices now
reaching nearly equal to the population of earth, embedded systems have truly
become ubiquitous. These trends, however, have also made the task of managing
their power consumption extremely challenging. In recent years, several
techniques have been proposed to address this issue. In this paper, we survey
the techniques for managing power consumption of embedded systems. We discuss
the need of power management and provide a classification of the techniques on
several important parameters to highlight their similarities and differences.
This paper is intended to help the researchers and application-developers in
gaining insights into the working of power management techniques and designing
even more efficient high-performance embedded systems of tomorrow
Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems
Recently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the fault-tolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone
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