209 research outputs found

    Adapting TDMA arbitration for measurement-based probabilistic timing analysis

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    Critical Real-Time Embedded Systems require functional and timing validation to prove that they will perform their functionalities correctly and in time. For timing validation, a bound to the Worst-Case Execution Time (WCET) for each task is derived and passed as an input to the scheduling algorithm to ensure that tasks execute timely. Bounds to WCET can be derived with deterministic timing analysis (DTA) and probabilistic timing analysis (PTA), each of which relies upon certain predictability properties coming from the hardware/software platform beneath. In particular, specific hardware designs are needed for both DTA and PTA, which challenges their adoption by hardware vendors. This paper makes a step towards reconciling the hardware needs of DTA and PTA timing analyses to increase the likelihood of those hardware designs to be adopted by hardware vendors. In particular, we show how Time Division Multiple Access (TDMA), which has been regarded as one of the main DTA-compliant arbitration policies, can be used in the context of PTA and, in particular, of the industrially-friendly Measurement-Based PTA (MBPTA). We show how the execution time measurements taken as input for MBPTA need to be padded to obtain reliable and tight WCET estimates on top of TDMA-arbitrated hardware resources with no further hardware support. Our results show that TDMA delivers tighter WCET estimates than MBPTA-friendly arbitration policies, whereas MBPTA-friendly policies provide higher average performance. Thus, the best policy to choose depends on the particular needs of the end user.The research leading to these results has been funded by the EU FP7 under grant agreement no. 611085 (PROXIMA) and 287519 (parMERASA). This work has also been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Miloˇs Pani´c is funded by the Spanish Ministry of Education under the FPU grant FPU12/05966. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.Peer ReviewedPostprint (author's final draft

    A time-predictable many-core processor design for critical real-time embedded systems

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    Critical Real-Time Embedded Systems (CRTES) are in charge of controlling fundamental parts of embedded system, e.g. energy harvesting solar panels in satellites, steering and breaking in cars, or flight management systems in airplanes. To do so, CRTES require strong evidence of correct functional and timing behavior. The former guarantees that the system operates correctly in response of its inputs; the latter ensures that its operations are performed within a predefined time budget. CRTES aim at increasing the number and complexity of functions. Examples include the incorporation of \smarter" Advanced Driver Assistance System (ADAS) functionality in modern cars or advanced collision avoidance systems in Unmanned Aerial Vehicles (UAVs). All these new features, implemented in software, lead to an exponential growth in both performance requirements and software development complexity. Furthermore, there is a strong need to integrate multiple functions into the same computing platform to reduce the number of processing units, mass and space requirements, etc. Overall, there is a clear need to increase the computing power of current CRTES in order to support new sophisticated and complex functionality, and integrate multiple systems into a single platform. The use of multi- and many-core processor architectures is increasingly seen in the CRTES industry as the solution to cope with the performance demand and cost constraints of future CRTES. Many-cores supply higher performance by exploiting the parallelism of applications while providing a better performance per watt as cores are maintained simpler with respect to complex single-core processors. Moreover, the parallelization capabilities allow scheduling multiple functions into the same processor, maximizing the hardware utilization. However, the use of multi- and many-cores in CRTES also brings a number of challenges related to provide evidence about the correct operation of the system, especially in the timing domain. Hence, despite the advantages of many-cores and the fact that they are nowadays a reality in the embedded domain (e.g. Kalray MPPA, Freescale NXP P4080, TI Keystone II), their use in CRTES still requires finding efficient ways of providing reliable evidence about the correct operation of the system. This thesis investigates the use of many-core processors in CRTES as a means to satisfy performance demands of future complex applications while providing the necessary timing guarantees. To do so, this thesis contributes to advance the state-of-the-art towards the exploitation of parallel capabilities of many-cores in CRTES contributing in two different computing domains. From the hardware domain, this thesis proposes new many-core designs that enable deriving reliable and tight timing guarantees. From the software domain, we present efficient scheduling and timing analysis techniques to exploit the parallelization capabilities of many-core architectures and to derive tight and trustworthy Worst-Case Execution Time (WCET) estimates of CRTES.Los sistemas críticos empotrados de tiempo real (en ingles Critical Real-Time Embedded Systems, CRTES) se encargan de controlar partes fundamentales de los sistemas integrados, e.g. obtención de la energía de los paneles solares en satélites, la dirección y frenado en automóviles, o el control de vuelo en aviones. Para hacerlo, CRTES requieren fuerte evidencias del correcto comportamiento funcional y temporal. El primero garantiza que el sistema funciona correctamente en respuesta de sus entradas; el último asegura que sus operaciones se realizan dentro de unos limites temporales establecidos previamente. El objetivo de los CRTES es aumentar el número y la complejidad de las funciones. Algunos ejemplos incluyen los sistemas inteligentes de asistencia a la conducción en automóviles modernos o los sistemas avanzados de prevención de colisiones en vehiculos aereos no tripulados. Todas estas nuevas características, implementadas en software,conducen a un crecimiento exponencial tanto en los requerimientos de rendimiento como en la complejidad de desarrollo de software. Además, existe una gran necesidad de integrar múltiples funciones en una sóla plataforma para así reducir el número de unidades de procesamiento, cumplir con requisitos de peso y espacio, etc. En general, hay una clara necesidad de aumentar la potencia de cómputo de los actuales CRTES para soportar nueva funcionalidades sofisticadas y complejas e integrar múltiples sistemas en una sola plataforma. El uso de arquitecturas multi- y many-core se ve cada vez más en la industria CRTES como la solución para hacer frente a la demanda de mayor rendimiento y las limitaciones de costes de los futuros CRTES. Las arquitecturas many-core proporcionan un mayor rendimiento explotando el paralelismo de aplicaciones al tiempo que proporciona un mejor rendimiento por vatio ya que los cores se mantienen más simples con respecto a complejos procesadores de un solo core. Además, las capacidades de paralelización permiten programar múltiples funciones en el mismo procesador, maximizando la utilización del hardware. Sin embargo, el uso de multi- y many-core en CRTES también acarrea ciertos desafíos relacionados con la aportación de evidencias sobre el correcto funcionamiento del sistema, especialmente en el ámbito temporal. Por eso, a pesar de las ventajas de los procesadores many-core y del hecho de que éstos son una realidad en los sitemas integrados (por ejemplo Kalray MPPA, Freescale NXP P4080, TI Keystone II), su uso en CRTES aún precisa de la búsqueda de métodos eficientes para proveer evidencias fiables sobre el correcto funcionamiento del sistema. Esta tesis ahonda en el uso de procesadores many-core en CRTES como un medio para satisfacer los requisitos de rendimiento de aplicaciones complejas mientras proveen las garantías de tiempo necesarias. Para ello, esta tesis contribuye en el avance del estado del arte hacia la explotación de many-cores en CRTES en dos ámbitos de la computación. En el ámbito del hardware, esta tesis propone nuevos diseños many-core que posibilitan garantías de tiempo fiables y precisas. En el ámbito del software, la tesis presenta técnicas eficientes para la planificación de tareas y el análisis de tiempo para aprovechar las capacidades de paralelización en arquitecturas many-core, y también para derivar estimaciones de peor tiempo de ejecución (Worst-Case Execution Time, WCET) fiables y precisas

    Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain

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    Critical Real-Time Embedded Systems (CRTES) follow a verification and validation process on the timing and functional correctness. This process includes the timing analysis that provides Worst-Case Execution Time (WCET) estimates to provide evidence that the execution time of the system, or parts of it, remain within the deadlines. A key design principle for CRTES is the incremental qualification, whereby each software component can be subject to verification and validation independently of any other component, with obvious benefits for cost. At timing level, this requires time composability, such that the timing behavior of a function is not affected by other functions. CRTES are experiencing an unprecedented growth with rising performance demands that have motivated the use of multicore architectures. Multicores can provide the performance required and bring the potential of integrating several software functions onto the same hardware. However, multicore contention in the access to shared hardware resources creates a dependence of the execution time of a task with the rest of the tasks running simultaneously. This dependence threatens time predictability and jeopardizes time composability. In this thesis we analyze and propose hardware solutions to be applied on current multicore designs for CRTES to improve time predictability and time composability, focusing on the on-chip bus and the memory controller. At hardware level, we propose new bus and memory controller designs that control and mitigate contention between different cores and allow to have time composability by design, also in the context of mixed-criticality systems. At analysis level, we propose contention prediction models that factor the impact of contenders and don¿t need modifications to the hardware. We also propose a set of Performance Monitoring Counters (PMC) that provide evidence about the contention. We give an special emphasis on the Space domain focusing on the Cobham Gaisler NGMP multicore processor, which is currently assessed by the European Space Agency for its future missions.Los Sistemas Críticos Empotrados de Tiempo Real (CRTES) siguen un proceso de verificación y validación para su correctitud funcional y temporal. Este proceso incluye el análisis temporal que proporciona estimaciones de el peor caso del tiempo de ejecución (WCET) para dar evidencia de que el tiempo de ejecución del sistema, o partes de él, permanecen dentro de los límites temporales. Un principio de diseño clave para los CRTES es la cualificación incremental, por la que cada componente de software puede ser verificado y validado independientemente del resto de componentes, con beneficios obvios para el coste. A nivel temporal, esto requiere composabilidad temporal, por la que el comportamiento temporal de una función no se ve afectado por otras funciones. CRTES están experimentando un crecimiento sin precedentes con crecientes demandas de rendimiento que han motivado el uso the arquitecturas multi-núcleo (multicore). Los procesadores multi-núcleo pueden proporcionar el rendimiento requerido y tienen el potencial de integrar varias funcionalidades software en el mismo hardware. A pesar de ello, la interferencia entre los diferentes núcleos que aparece en los recursos compartidos de os procesadores multi núcleo crea una dependencia del tiempo de ejecución de una tarea con el resto de tareas ejecutándose simultáneamente en el procesador. Esta dependencia amenaza la predictabilidad temporal y compromete la composabilidad temporal. En esta tésis analizamos y proponemos soluciones hardware para ser aplicadas en los diseños multi núcleo actuales para CRTES que mejoran la predictabilidad y composabilidad temporal, centrándose en el bus y el controlador de memoria internos al chip. A nivel de hardware, proponemos nuevos diseños de buses y controladores de memoria que controlan y mitigan la interferencia entre los diferentes núcleos y permiten tener composabilidad temporal por diseño, también en el contexto de sistemas de criticalidad mixta. A nivel de análisis, proponemos modelos de predicción de la interferencia que factorizan el impacto de los núcleos y no necesitan modificaciones hardware. También proponemos un conjunto de Contadores de Control del Rendimiento (PMC) que proporcionoan evidencia de la interferencia. En esta tésis, damós especial importancia al dominio espacial, centrándonos en el procesador mutli núcleo Cobham Gaisler NGMP, que está siendo actualmente evaluado por la Agencia Espacial Europea para sus futuras misiones

    Design Approach to Implementation Of Arbitration Algorithm In Shared Bus Architectures (MPSoC)

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    The multiprocessor SoC designs have more than one processor and huge memory on the same chip. SoC consists of hardware cores and software cores ,multiple processors, embedded DRAM and connectors between cores .A wide range of MPSOC architectures have been developed over the past decade. This paper surveys the history of various On-Chip communication architectures present in the design of MPSoC. This acts as a primary factor of overall performance in complex SoC designs. Some of the various techniques that have driven the design of MpSoC has been discussed. Dynamically configurable communication architectures are found to improve the system performance. Currently On-chip interconnection networks are mostly implemented using shared buses which are the most common medium. The arbitration plays a crucial role in determining performance of bus-based system, as it assigns priorities, with which processor is granted the access to the shared communication resources. In the conventional arbitration algorithms there are some drawbacks such as bus starvation problem and low system performance. The bus should provide each component a flexible and utmost share of on-chip communication bandwidth and should improve the latency in access of the shared bus. The performance of SoC is improved using the probabilistic round robin algorithm with regard to the parameters, latency.Thus in this paper various issues related to bus arbitration related to design of MPSoC is analysed

    Using the ethernet protocol for real-time communications in embedded systems

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    Doutoramento em Engenharia ElectrotécnicaOs Sistemas Computacionais de Controlo Distribuído (SCCD) estão muito disseminados em aplicações que vão desde o controlo de processos e manufactura a automóveis, aviões e robôs. Muitas aplicações são de natureza tempo-real, ou seja, impõem fortes restrições às propriedades subjacentes aos sistemas de controlo, gerando a necessidade de fornecer um comportamento temporal previsível durante períodos alargados de tempo. Em particular, dependendo da aplicação, uma falha em garantir as restrições pode causar importantes perdas económicas ou mesmo pôr vidas humanas em risco. Actualmente, a quantidade e funcionalidade dos modernos SCCD têm crescido firmemente. Esta evolução é motivada por uma nova classe de aplicações que requer maior demanda de recursos tais como aplicações de multimedia (por exemplo visão), bem como pela tendência em usar grande número de processadres simples e interconectados, em vez de poucos e poderosos processadores, encapsulando cada funcionalidade num único processador. Consequentemente, a quantidade de informação que deve ser trocada entre os nós da rede também cresceu drasticamente nos últimos anos e está agora atingindo os limites que podem ser obtidos por tradicionais barramentos de campo, como por exempo CAN, WorldFIP, PROFIBUS. Outras alternativas são pois requeridas para suportar a necessidade de largura de banda e a manutenção de exigências dos sistemas de comunicação tempo-real: previsibilidade, pontualidade, atraso e variação de período limitados. Uma das linhas de trabalho tem apostado na Ethernet, tirando vantagem dos baixos custos dos circuitos, da elevada largura de banda, da fácil integração com a Internet, e da simplicidade em promover expansões e compatibilidade com redes usadas na estrutura administrativa das empresas industriais. Porém, o mecanismo padronizado de acesso ao meio da Ethernet (CSMA/CD) é destrutivo e não determinístico, o que impede seu uso directo ao nível de campo ou pelo menos em aplicações de comunicação tempo-real. Apesar disso, muitas abordagens diferentes têm sido propostas e usadas para obter comportamento tempo-real em Ethernet. As abordagens actuais para dotar de comportamento tempo-real Ethernet partilhada apresentam desvantagens tais como: exigência de hardware especializado, fornecimento de garantias temporais estatísticas, ineficiência na utilização da largura de banda ou na reposta tempo-real. São ainda por vezes inflexíveis com respeito às propriedades de tráfego bem como com as políticas de escalonamento. Podem exigir processadores com elevado poder de cálculo. Finalmente não permitem que estações tempo-real possam coexistir com estações Ethernet standard no mesmo segmento. Uma proposta recente, o algoritmo hBEB, permite a coexistência de estações tempo-real e standard no mesmo segmento. Contudo, apenas uma estação tempo-real pode estar activa, o que é inaceitável para aplicações de automação e controlo. Esta tese discute uma nova solução para promover tempo-real em Ethernet partilhada, baseando-se na passagem implícita de testemunho de forma similar à usada pelo protocolo P-NET. Esta técnica é um mecanismo de acesso ao meio físico pouco exigente em termos de processamento, sendo portanto adequada para implementar uma rede de dispositivos baseados em processadores de baixo poder de cálculo e controladores Ethernet standard. Esta tese apresenta ainda uma proposta de implementação do VTPE em IP core para superar algumas dificuldades derivadas de funcionalidades que não são suportadas por controladores standard, nomeadamente a arbitragem do meio físico durante a transmissão de uma trama. Esta nova proposta pode aumentar muito a eficiência do VTPE no uso da largura de banda. O VTPE, assim como P-NET ou protocolos similares, permite a uma estação apenas comunicar uma vez por cada circulação do testemunho. Esta imposição pode causar bloqueios de comunicação por períodos inaceitáveis em aplicações com tráfego isócrono, por exemplo multimedia. Uma solução proposta permite que uma estação possa aceder ao meio físico mais de uma vez por cada circulação do token. Os resultados experimentais a as análises desenvolvidas mostram que o bloqueio pode ser drasticamente reduzido. Por último esta tese discute uma variante do protocolo VTPE, o VTPE/h- BEB, que permite que mais de uma estação hBEB possa coexistir com diversas estações Ethernet standard num mesmo segmento partilhado. Um demonstrador para prova de conceito bem como uma aplicação foram também implementados.Distributed Computer-Control Systems (DCCS) are widely disseminated in applications ranging from automation and control to automotive, avionics and robotics. Many of these applications are real-time, posing stringent constraints to the properties of underlying control systems, which arise from the need to provide predictable behaviour during extended time periods. Depending on the particular type of application, a failure to meet these constraints can cause important economic losses or can even put human life in risk. Currently the number and functionality of modern DCCSs have been increasing steadily. This evolution has been motivated for a new class of applications of more resource demanding applications, such as multimedia (e.g. machine vision), as well as by the trend to use large numbers of simple interconnected processors, instead of a few powerful ones, encapsulating each functionality in one single processor. Consequently, the amount of information that must be exchanged among the network nodes has also increased dramatically and is now reaching the limits achievable by traditional fieldbuses. Therefore, other alternatives are required to support higher bandwidth demands while keeping the main requirements of a real-time communication system: predictability, timeliness, bounded delays and jitter. Efforts have been made with Ethernet to take advantage of the low cost of the silicon, high bandwidth, easy integration with the Internet, easy expansion and compatibility with the networks used at higher layers in the factory structure. However its standardized media access control (CSMA/CD) is destructive and not deterministic, impairing its direct use at field level at least for real-time communication. Despite this, many solutions have been proposed to achieve real-time behavior in Ethernet. However they present several disadvantages: requiring specialized hardware, providing statistical timeliness guarantees only, being bandwidth or response-time inefficient, being inflexible concerning traffic properties and/or scheduling policy, or finally not allowing real-time stations to coexist with standard Ethernet stations in the same segment. A recent proposal, the hBEB algorithm, allows the coexistence of real-time and standard Ethernet stations in the same shared segment. However hBEB limits at most one real-time station per segment which is unacceptable for applications in industrial automation and process control. This thesis discusses a new real-time shared Ethernet solution based on the virtual token passing technique similarly to the one used by the P-NET protocol. This technique is a medium access control mechanism that requires small processing power, being suitable to implement devices based on processors with small processing power. The solution is called Virtual Token Passing Ethernet or VTPE. This proposal discusses the modifications required in the Ethernet frame format, the temporal analysis to guarantee real-time communication and the implementation of two demonstrators based on microcontrollers and standard Ethernet controllers. This thesis also presents a proposal to implement VTPE in an IP Core to overcome some difficulties derived from limitations of standard Ethernet controllers, namely to allow medium access control during a frame transmission. This proposal can increase the bandwidth efficiency of VTPE. VTPE, as well as P-NET or any other protocol based on circular token rotation technique, only allows a station to communicate once for each token round. This design imposition can cause unacceptable communication blocking in applications with isochronous traffic such as multimedia. An improvement in the VTPE proposal enables a station to access the medium more than once per token round. The experimental results as well as the temporal analysis show that the blocking can be drastically reduced. This improvement can also be used in the P-NET protocol. Finally this thesis proposes a variant of VTPE, named VTPE/hBEB, to be implemented in Ethernet controllers that are able to support the hBEB algorithm. The VTPE/hBEB allows more than one hBEB station to coexist with several standard Ethernet stations in the same shared Ethernet segment. A demonstrator for the VTPE/hBEB validation, as well as an application, are also presented and discussed

    Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey

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    "© ACM, 2019. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in ACM Computing Surveys, {VOL 52, ISS 1, (February 2019)} https://dl.acm.org/doi/10.1145/3301283"[EN] The unabated increase in the complexity of the hardware and software components of modern embedded real-time systems has given momentum to a host of research in the use of probabilistic and statistical techniques for timing analysis. In the last few years, that front of investigation has yielded a body of scientific literature vast enough to warrant some comprehensive taxonomy of motivations, strategies of application, and directions of research. This survey addresses this very need, singling out the principal techniques in the state of the art of timing analysis that employ probabilistic reasoning at some level, building a taxonomy of them, discussing their relative merit and limitations, and the relations among them. In addition to offering a comprehensive foundation to savvy probabilistic timing analysis, this article also identifies the key challenges to be addressed to consolidate the scientific soundness and industrial viability of this emerging field.This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773), and the HiPEAC Network of Excellence. Jaume Abella was partially supported by the Ministry of Economy and Competitiveness under a Ramon y Cajal postdoctoral fellowship (RYC-2013-14717). Enrico Mezzetti has been partially supported by the Spanish Ministry of Economy and Competitiveness under Juan de la Cierva-Incorporación postdoctoral fellowship No. IJCI-2016-27396.Cazorla, FJ.; Kosmidis, L.; Mezzetti, E.; Hernández Luz, C.; Abella, J.; Vardanega, T. (2019). Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey. ACM Computing Surveys. 52(1):1-35. https://doi.org/10.1145/3301283S13552

    Sub-GHz LPWAN network coexistence, management and virtualization : an overview and open research challenges

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    The IoT domain is characterized by many applications that require low-bandwidth communications over a long range, at a low cost and at low power. Low power wide area networks (LPWANs) fulfill these requirements by using sub-GHz radio frequencies (typically 433 or 868 MHz) with typical transmission ranges in the order of 1 up to 50 km. As a result, a single base station can cover large areas and can support high numbers of connected devices (> 1000 per base station). Notorious initiatives in this domain are LoRa, Sigfox and the upcoming IEEE 802.11ah (or "HaLow") standard. Although these new technologies have the potential to significantly impact many IoT deployments, the current market is very fragmented and many challenges exists related to deployment, scalability, management and coexistence aspects, making adoption of these technologies difficult for many companies. To remedy this, this paper proposes a conceptual framework to improve the performance of LPWAN networks through in-network optimization, cross-technology coexistence and cooperation and virtualization of management functions. In addition, the paper gives an overview of state of the art solutions and identifies open challenges for each of these aspects

    A Survey of Probabilistic Timing Analysis Techniques for Real-Time Systems

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    This survey covers probabilistic timing analysis techniques for real-time systems. It reviews and critiques the key results in the field from its origins in 2000 to the latest research published up to the end of August 2018. The survey provides a taxonomy of the different methods used, and a classification of existing research. A detailed review is provided covering the main subject areas: static probabilistic timing analysis, measurement-based probabilistic timing analysis, and hybrid methods. In addition, research on supporting mechanisms and techniques, case studies, and evaluations is also reviewed. The survey concludes by identifying open issues, key challenges and possible directions for future research
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