2,658 research outputs found

    Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

    Get PDF
    In recent technology nodes, reliability is considered a part of the standard design ¿ow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approac

    Design and Control of Power Converters 2020

    Get PDF
    In this book, nine papers focusing on different fields of power electronics are gathered, all of which are in line with the present trends in research and industry. Given the generality of the Special Issue, the covered topics range from electrothermal models and losses models in semiconductors and magnetics to converters used in high-power applications. In this last case, the papers address specific problems such as the distortion due to zero-current detection or fault investigation using the fast Fourier transform, all being focused on analyzing the topologies of high-power high-density applications, such as the dual active bridge or the H-bridge multilevel inverter. All the papers provide enough insight in the analyzed issues to be used as the starting point of any research. Experimental or simulation results are presented to validate and help with the understanding of the proposed ideas. To summarize, this book will help the reader to solve specific problems in industrial equipment or to increase their knowledge in specific fields

    Fault current limiting and protection circuit for power electronics used in a Modular Converter

    Get PDF
    The thesis objective is to safeguard power electronics used in modular converter applications. A new fault current limiting and protection circuit is proposed. The system level fault mitigation assemblies take a long time to remove a fault and within this time the IGBTs used in the Flexible AC Transmission System (FACTS) application will undergo high thermal and mechanical stress. Exposure to such conditions over a prolonged period of time will reduce the device lifetime, which is one of the major reasons why power electronics are not very popular in utility applications. Modular converter approach will reduce the device ratings required to mitigate the fault at power electronics level. The fault current limiting and protection circuit is tested using PSPICE simulation tool. The test set up is simple comprising of two IGBTs, one which acts as device under test (DUT) and another which acts as switch regulating fault seen by DUT. The test voltage is 480 Volt and R-L is varied over a range of L – 20nanoHenry, 2microHenry, and 10microHenry and R – 20Ohm, 50Ohm, and 100Ohm. The fault current limiting (FCL) and protection circuit worked accurately in each of the cases described above, thereby safely turning OFF the device within the short circuit withstand capacity (10microseconds) of IGBTs. The FCL and protection circuit can mitigate both Hard Switched Fault and Fault Under Load seen by the IGBT during short circuit condition. The circuit developed is different from the conventional protection gate drives available in the market and there is the possibility of customizing it further for modular blocks

    A Hybrid Method of Performing Electric Power System Fault Ride-Through Evaluations on Medium Voltage Multi-Megawatt Devices

    Get PDF
    This dissertation explores the design and analysis of a Hybrid Method of performing electrical power system fault ride-through evaluations on multi-megawatt, medium voltage power conversion equipment. Fault ride-through evaluations on such equipment are needed in order to verify and validate full scale designs prior to being implemented in the field. Ultimately, these evaluations will help in reducing the deployment risks associated with bringing new technologies into the marketplace. This is especially true for renewable energy and utility scale energy storage systems, where a significant amount of attention in recent years has focused on their ever increasing role in power system security and stability. The Hybrid Method couples two existing technologies together - a reactive voltage divider network and a power electronic variable voltage source - in order to overcome the inherent limitation of both methods, namely the short circuit duty required for implementation. This work provides the background of this limitation with respect to the existing technologies and demonstrates that the Hybrid Method can minimize the fault duty required for fault evaluations. The physical system, control objectives, and operation cycle of the Hybrid Method are analyzed with respect to the overall objective of reducing the fault duty of the system. A vector controller is designed to incorporate the time variant nature of the Hybrid Method operation cycle, limit the fault current seen by the power electronic variable voltage source, and provide regulation of the voltage at the point of common coupling with the device being evaluated. In order to verify the operation of both the Hybrid Method physical system and vector controller, a controller hardware-in-the-loop experiment is created in order to simulate the physical system in real-time against the prototype implementation of the vector controller. The physical system is simulated in a Real Time Digital Simulator and is controlled with the Hybrid Method vector controller implemented on a National Instruments FPGA. In order to evaluate the complete performance of the Hybrid Method, both a synchronous generator and a doubly-fed induction generator are modeled as the device under test in the simulations of the physical system. Finally, the results of the controller hardware-in-the-loop experiments are presented which demonstrate that the Hybrid Method is a viable solution to performing fault ride-through evaluations on multi-megawatt, medium voltage power conversion equipment

    Study and evaluation of distributed power electronic converters in photovoltaic generation applications

    Get PDF
    This research project has proposed a new modulation technique called “Local Carrier Pulse Width Modulation” (LC-PWM) for MMCs with different cell voltages, taking into account the measured cell voltages to generate switching sequences with more accurate timing. It also adapts the modulator sampling period to improve the transitions from level to level, an important issue to reduce noise at the internal circulating currents. As a result, the new modulation LC-PWM technique reduces the output distortion in a wider range of voltage situations. Furthermore, it effectively eliminates unnecessary AC components of circulating currents, resulting in lower power losses and higher MMC efficiency.Departamento de Tecnología ElectrónicaDoctorado en Ingeniería Industria

    Cascaded- and Modular-Multilevel Converter Laboratory Test System Options: A Review

    Get PDF
    The increasing importance of cascaded multilevel converters (CMCs), and the sub-category of modular multilevel converters (MMCs), is illustrated by their wide use in high voltage DC connections and in static compensators. Research is being undertaken into the use of these complex pieces of hardware and software for a variety of grid support services, on top of fundamental frequency power injection, requiring improved control for non-traditional duties. To validate these results, small-scale laboratory hardware prototypes are often required. Such systems have been built by many research teams around the globe and are also increasingly commercially available. Few publications go into detail on the construction options for prototype CMCs, and there is a lack of information on both design considerations and lessons learned from the build process, which will hinder research and the best application of these important units. This paper reviews options, gives key examples from leading research teams, and summarizes knowledge gained in the development of test rigs to clarify design considerations when constructing laboratory-scale CMCs.This work was supported in part by The University of Manchester supported by the National Innovation Allowance project ``VSC-HVDC Model Validation and Improvement'' and Dr. Heath's iCASE Ph.D. studentship supported through Engineering and Physical Sciences Research Council (EPSRC) and National Grid, in part by the Imperial College London supported by EPSRC through the HubNet Extension under Grant EP/N030028/1, in part by an iCASE Ph.D. Studentship supported by EPSRC and EDF Energy and the CDT in Future Power Networks under Grant EP/L015471/1, in part by University of New South Wales (UNSW) supported by the Solar Flagships Program through the Education Infrastructure Fund (EIF), in part by the Australian Research Council through the Discovery Early Career Research Award under Grant DECRA_DE170100370, in part by the Basque Government through the project HVDC-LINK3 under Grant ELKARTEK KK-2017/00083, in part by the L2EP research group at the University of Lille supported by the French TSO (RTE), and in part by the Hauts-de-France region of France with the European Regional Development Fund under Grant FEDER 17007725

    C-MOS array design techniques: SUMC multiprocessor system study

    Get PDF
    The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units

    Real-Time Machine Learning Based Open Switch Fault Detection and Isolation for Multilevel Multiphase Drives

    Get PDF
    Due to the rapid proliferation interest of the multiphase machines and their combination with multilevel inverters technology, the demand for high reliability and resilient in the multiphase multilevel drives is increased. High reliability can be achieved by deploying systematic preventive real-time monitoring, robust control, and efficient fault diagnosis strategies. Fault diagnosis, as an indispensable methodology to preserve the seamless post-fault operation, is carried out in consecutive steps; monitoring the observable signals to generate the residuals, evaluating the observations to make a binary decision if any abnormality has occurred, and identifying the characteristics of the abnormalities to locate and isolate the failed components. It is followed by applying an appropriate reconfiguration strategy to ensure that the system can tolerate the failure. The primary focus of presented dissertation was to address employing computational and machine learning techniques to construct a proficient fault diagnosis scheme in multilevel multiphase drives. First, the data-driven nonlinear model identification/prediction methods are used to form a hybrid fault detection framework, which combines module-level and system-level methods in power converters, to enhance the performance and obtain a rapid real-time detection. Applying suggested nonlinear model predictors along with different systems (conventional two-level inverter and three-level neutral point clamped inverter) result in reducing the detection time to 1% of stator current fundamental period without deploying component-level monitoring equipment. Further, two methods using semi-supervised learning and analytical data mining concepts are presented to isolate the failed component. The semi-supervised fuzzy algorithm is engaged in building the clustering model because the deficient labeled datasets (prior knowledge of the system) leads to degraded performance in supervised clustering. Also, an analytical data mining procedure is presented based on data interpretability that yields two criteria to isolate the failure. A key part of this work also dealt with the discrimination between the post-fault characteristics, which are supposed to carry the data reflecting the fault influence, and the output responses, which are compensated by controllers under closed-loop control strategy. The performance of all designed schemes is evaluated through experiments

    Studies of Uncertainties in Smart Grid: Wind Power Generation and Wide-Area Communication

    Get PDF
    This research work investigates the uncertainties in Smart Grid, with special focus on the uncertain wind power generation in wind energy conversion systems (WECSs) and the uncertain wide-area communication in wide-area measurement systems (WAMSs). For the uncertain wind power generation in WECSs, a new wind speed modeling method and an improved WECS control method are proposed, respectively. The modeling method considers the spatial and temporal distributions of wind speed disturbances and deploys a box uncertain set in wind speed models, which is more realistic for practicing engineers. The control method takes maximum power point tracking, wind speed forecasting, and wind turbine dynamics into account, and achieves a balance between power output maximization and operating cost minimization to further improve the overall efficiency of wind power generation. Specifically, through the proposed modeling and control methods, the wind power control problem is developed as a min-max optimal problem and efficiently solved with semi-definite programming. For the uncertain communication delay and communication loss (i.e. data loss) in WAMSs, the corresponding solutions are presented. First, the real-world communication delay is measured and analyzed, and the bounded modeling method for the communication delay is proposed for widearea applications and further applied for system-area and substation-area protection applications, respectively. The proposed bounded modeling method is expected to be an important tool in the planning, design, and operation of time-critical wide-area applications. Second, the real synchronization signal loss and synchrophasor data loss events are measured and analyzed. For the synchronization signal loss, the potential reasons and solutions are explored. For the synchrophasor data loss, a set of estimation methods are presented, including substitution, interpolation, and forecasting. The estimation methods aim to improve the accuracy and availability of WAMSs, and mitigate the effect of communication failure and data loss on wide-area applications

    High Power Density and High Efficiency Converter Topologies for Renewable Energy Conversion and EV Applications

    Get PDF
    This dissertation work presents two novel converter topologies (a three-level ANPC inverter utilizing hybrid Si/SiC switches and an Asymmetric Alternate Arm Converter (AAAC) topology) that are suitable for high efficiency and high-power density energy conversion systems. The operation principle, modulation, and control strategy of these newly introduced converter topologies are presented in detail supported by simulation and experimental results. A thorough design optimization of these converter topologies (Si/SiC current rating ratio optimization and gate control strategies for the three-level ANPC inverter topology and component sizing for the asymmetric alternate arm converter topology) are also presented. Performance comparison of the proposed converter topologies with other similar converter topologies is also presented. The performance of the proposed ANPC inverter topology is compared with other ANPC inverter topologies such as an all SiC MOSFET ANPC inverter topology, an all Si IGBT ANPC inverter topology and mixed Si IGBT and SiC MOSFET based ANPC inverter topologies in terms of efficiency and cost. The efficiency and cost comparison results show that the proposed hybrid Si/SiC switch based ANPC inverter has higher efficiency and lower cost compared to the other ANPC inverter topologies considered for the comparison. The performance of the asymmetric alternate arm converter topology is also compared with other similar voltage source converter topologies such as the modular multilevel converter topology, the alternate arm converter topology, and the improved alternate arm converter topology in terms of total device count, number of switches per current conduction path, output voltage levels, dc-fault blocking capability and overmodulation capability. The proposed multilevel converter topology has lower total number of devices and lower number of devices per current conduction path hence it has lower cost and lower conduction power loss. However, it has lower number of output voltage levels (requiring larger ac interface inductors) and lacks dc-fault blocking and overmodulation operation capabilities. A converter figure-of-merit accounting for the hybrid Si/SiC switch and converter topology properties is also proposed to help perform quick performance comparison between different hybrid Si/SiC switch based converter topologies. It eliminates the need for developing full electro-thermal power loss model for different converter topologies that would otherwise be needed to carry out power loss comparison between different converter topologies. Hence it saves time and effort
    corecore