3,468 research outputs found
Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip
The ATLAS Collaboration will upgrade its semiconductor pixel tracking
detector with a new Insertable B-layer (IBL) between the existing pixel
detector and the vacuum pipe of the Large Hadron Collider. The extreme
operating conditions at this location have necessitated the development of new
radiation hard pixel sensor technologies and a new front-end readout chip,
called the FE-I4. Planar pixel sensors and 3D pixel sensors have been
investigated to equip this new pixel layer, and prototype modules using the
FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN
SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test
results are presented, including charge collection efficiency, tracking
efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
Single-Photon Avalanche Diodes in a 0.16 ÎĽm BCD Technology With Sharp Timing Response and Red-Enhanced Sensitivity
CMOS single-photon avalanche diodes (SPADs) have recently become an emerging imaging technology for applications requiring high sensitivity and high frame-rate in the visible and near-infrared range. However, a higher photon detection efficiency (PDE), particularly in the 700-950 nm range, is highly desirable for many growing markets, such as eye-safe three-dimensional imaging (LIDAR). In this paper, we report the design and characterization of SPADs fabricated in a 0.16 mu m BCD (Bipolar-CMOS-DMOS) technology. The overall detection performance is among the best reported in the literature: 1) PDE of 60% at 500 nm wavelength and still 12% at 800 nm; 2) very low dark count rate of < 0.2 cps/mu m(2) (in counts per second per unit area); 3) < 1% afterpulsing probability with 50 ns dead-time; and 4) temporal response with 30 ps full width at half-maximum and less than 50 ps diffusion tail time constant
Design and Characterization of CMOS/SOI Image Sensors
The design, operation, and characterization of CMOS imagers implemented using: 1) regular CMOS wafers with a 0.5-mum CMOS analog process; 2) regular CMOS wafers with a 0.35-mum CMOS analog process; and 3) silicon-on-insulator (SOI) wafers in conjunction with a 0.35-mum CMOS analog process, are discussed in this paper. The performances of the studied imagers are compared in terms of quantum efficiency, dark current, and optical bandwidth. It is found that there is strong dependence of quantum efficiency of the photodiodes on the architecture of the image sensor. The results of this paper are useful for designing and modeling CMOS/SOI image sensor
The low area probing detector as a countermeasure against invasive attacks
© 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksMicroprobing allows intercepting data from on-chip wires as well as injecting faults into data or control lines. This makes it a commonly used attack technique against security-related semiconductors, such as smart card controllers. We present the low area probing detector (LAPD) as an efficient approach to detect microprobing. It compares delay differences between symmetric lines such as bus lines to detect timing asymmetries introduced by the capacitive load of a probe. Compared with state-of-the-art microprobing countermeasures from industry, such as shields or bus encryption, the area overhead is minimal and no delays are introduced; in contrast to probing detection schemes from academia, such as the probe attempt detector, no analog circuitry is needed. We show the Monte Carlo simulation results of mismatch variations as well as process, voltage, and temperature corners on a 65-nm technology and present a simple reliability optimization. Eventually, we show that the detection of state-of-the-art commercial microprobes is possible even under extreme conditions and the margin with respect to false positives is sufficient.Peer ReviewedPostprint (author's final draft
A Resistive Voltage Divider for Power Measurements
The paper presents a resistive voltage divider (RVD), developed for power measurements at much higher frequencies than the traditional 50 Hz. The
design of the RVD and the methods of its evaluation are described. The RVD is intended to be used in a digital sampling wattmeter application based
on National Instruments PXI-4461 Dynamic Signal Analyzer. The design of the divider includes individual copper guards for each resistor, driven by
the auxiliary chain of resistors. To reduce the leakage currents, the PTFE terminals are applied between pins of the resistors and the printed circuit
board
A Resistive Voltage Divider for Power Measurements
The paper presents a resistive voltage divider (RVD), developed for power measurements at much higher frequencies than the traditional 50 Hz. The
design of the RVD and the methods of its evaluation are described. The RVD is intended to be used in a digital sampling wattmeter application based
on National Instruments PXI-4461 Dynamic Signal Analyzer. The design of the divider includes individual copper guards for each resistor, driven by
the auxiliary chain of resistors. To reduce the leakage currents, the PTFE terminals are applied between pins of the resistors and the printed circuit
board
45-nm Radiation Hardened Cache Design
abstract: Circuits on smaller technology nodes become more vulnerable to radiation-induced upset. Since this is a major problem for electronic circuits used in space applications, designers have a variety of solutions in hand. Radiation hardening by design (RHBD) is an approach, where electronic components are designed to work properly in certain radiation environments without the use of special fabrication processes. This work focuses on the cache design for a high performance microprocessor. The design tries to mitigate radiation effects like SEE, on a commercial foundry 45 nm SOI process. The design has been ported from a previously done cache design at the 90 nm process node. The cache design is a 16 KB, 4 way set associative, write-through design that uses a no-write allocate policy. The cache has been tested to write and read at above 2 GHz at VDD = 0.9 V. Interleaved layout, parity protection, dual redundancy, and checking circuits are used in the design to achieve radiation hardness. High speed is accomplished through the use of dynamic circuits and short wiring routes wherever possible. Gated clocks and optimized wire connections are used to reduce power. Structured methodology is used to build up the entire cache.Dissertation/ThesisM.S. Electrical Engineering 201
- …