FPGA embedded system for ultrasonic non-destructive testing

This thesis was submitted for the award of Doctor of Philosophy and was awarded by Brunel University LondonLong Range Ultrasonic Testing (LRUT) is an emerging ultrasound Non-destructive Testing (NDT) method. The LRUT is a variant of the conventional NDT approach. By using ultrasound guided waves (UGWs) , it is efficient in quick long range defect scanning, which is impossible with other traditional NDT techniques. Increasing numbers of requirements for quick long range testing have led to urgent need for the improvement of testing methods and the development of new testing equipment to help researchers in laboratory and help technicians in field inspection. The market for multi-channel ultrasonic instruments is characterized by small volumes of sales and a high ratio of development costs to sale price. The consequence is that the investment required to develop an instrument is significant and upgrades and other changes to instrument specification or configuration are difficult for many manufacturers to justify. These factors are particularly relevant for long range guided wave technology, where the technology is still relatively new in the market place and the instrumentation has different characteristics from other type of ultrasonic systems. In order to support the design and manufacture of the Teletest®MK4 system, Plant Integrity Ltd has supported this study into the use of a field-programmable gates array (FPGA) based control circuits for the electronics, which allows the component count to be decreased and also permits the system to be modified via flexible reconfiguration of the FPGA. This has benefits of reduction of size, weight and power consumption of the electronics and provides a means of upgrading the product without expensive re-design of the hardware. FPGA device has been the enabling technology and main thrust behind the evolution of many technologies, unleashing new opportunities for improving the performance of the LRUT equipment and providing more functions for industrial and academic applications. A novel system has been developed to provide multichannel waveform generation, data capture and signal processing for advanced lab-based research and faster- field testing. This system includes an FPGA to process multichannel data in parallel and to provide the flexibility of reconfiguration for various testing applications proposed by new research. The design was tested in pre-prototype hardware. Subsequent construction of the commercial prototype unit enabled successful operation of the design to be demonstrated. Implementation of the FPGA design reduced component count, PCB dimensions and power consumption. Though the SpartanTM 3A DSP FPGA and Xilinx ISE software have been used in this project, the concepts of the design can be applied to other FPGA devices from other FPGA vendors using other design softwares.TWI Ltd; Plant Integrity Lt

Development of Extrospective Systems for Mobile Robotic Vehicles.

Extrospection is the process of receiving knowledge of the outside world through the senses. On robotic platforms this is primarily focussed on determining distances to objects of interest and is achieved through the use of ranging sensors. Any hardware implemented on mobile robotic platforms, including sensors, must ideally be small in size and weight, have good power efficiency, be self-contained and interface easily with the existing platform hardware. The development of stable, expandable and interchangeable mobile robot based sensing systems is crucial to the establishment of platforms on which complex robotic research can be conducted and evaluated in real world situations. This thesis details the design and development of two extrospective systems for incorporation in the Victoria University of Wellington's fleet of mobile robotic platforms. The first system is a generic intelligent sensor network. Fundamental to this system has been the development of network architecture and protocols that provide a stable scheme for connecting a large number of sensors to a mobile robotic platform with little or no dependence on the existing hardware configuration of the platform. A prototype sensor network comprising fourteen infrared position sensitive detectors providing a short to medium distance ranging system (0.2 - 3 m) with a 360' field of view has been successfully developed and tested. The second system is a redesign of an existing prototype full-field image ranger system. The redesign has yielded a smaller, mobile version of the prototype system capable of ranging medium to long distances (0 - 15 m) with a 22.2' - 16.5' field-of-view. This ranger system can now be incorporated onto mobile robotic platforms for further research into the capabilities of full-field image ranging as a form of extrospection on a mobile platform

Digital Beamforming Implementation on an FPGA Platform

This work is part of UPC contribution to the CORPA (Cost-Optimised high Performance Active Receive Phase Array antenna for mobile terminals) project of ESA (European Space Agency)The objective of the work presented is to implement a Digital Beamforming (DBF) platform for an antenna array receiver designed for the S-DMB system. Our project deals with the design of antenna arrays from a hardware point of view, in contrast to other theo- retic studies regarding DBF algorithms. Hence, we will study practical aspects of DBF implementation such as signal quantization and required computational resources

Active Buffer Development in CBM Experiment

Die Anforderungen an das Datenerfassungssystem (DAQ) des CBM Experiments an der GSI sind mit einer Datenrate von 1TB/s und einer Ereignisrate von 100 kHz sehr hoch und stellen auch im Vergleich zu anderen Experimenten in der Hochenergiephysik eine Herausforderung dar. Bei der Datennahme wird daher ein aktiver Zwischenspeicher („active buffer“) eingesetzt, der durch eine Vorsortierung der Datenfragmente und eine intelligente Übertragung in den Hostrechner den Aufbau der Datenstrukturen zur Ereignisverarbeitung unterstützt. Das Projekt erfordert ein modulares Framework und die Arbeit umfasst die Entwicklung, Verifikation und Test von FPGA Modulen zum effizienten Datentransfer, zur Zwischenspeicherung und zur Rekonfiguration, sowie von Software zur automatischen Transformation von HDL Beschreibungen. Die zentralen Bauteile dieses Zwischenspeichers sind ein leistungsfähiges FPGA zur Datenflusssteuerung und ein DDR2 SDRAM Modul mit einer Kapazität von 512MB. Durch eine spezielle Ansteuerungsmethode kann das Speichermodul zusammen mit den FPGA-internen Speicherelementen als leistungsfähiges, großes FIFO betrieben werden. Den Datantransfer vom Zwischenspeicher zum PC übernimmt eine spezielle DMA Einheit, die an den PCIe-Kern im FPGA angeschlossen ist. Die zwei DMA Kanäle arbeiten mit Scatter-Gather Unterstützung und erreichen beim Transfer zum PC 543 MB/s und in der Gegenrichtung 790MB/s. Die für die Vorsortierung wichtige Übertragung der Zeitstempel („epoch marker“) erfolgt ebenfalls mit einem DMA Kanal. Die Verifikation ist eine wichtige Stufe bei der Entwicklung einer umfangreichen FPGA Anwendungen wie des aktiven Zwischenspeichers. Daher wurden die HDL Module der Funktionen für das PCI Express „transaction layer“ mit einer Reihe unterschiedlicher Simulationsumgebungen verifiziert. Auf dieser Grundlage können Verbesserungen an der Funktionalität schnell und zuverlässig umgesetzt werden, womit eine konsistente Weiterentwicklung gewährleistet ist. Aufgrund der typischen PC-Architektur muss die PCIe-Einheit im FPGA bereits während des Startvorgangs funktionsfähig sein, wohingegen die eigentliche aktive Zwischenspeicherfunktion erst zusammen mit der entsprechenden Anwendungssoftware verfügbar sein muss. Strikte Modularisierung zusammen mit dynamischer, partieller Rekonfigurierung („DPR“) ermöglichen Veränderungen in der Zwischenspeicherfunktion zur Laufzeit. Ein weiter Grund für die Nutzung der DPR sind die Lizenzbedingungen der PCIe-Core-Implementierung mit Virtex4-FPGAs. DPR kann bei den FPGA Familien Virtex-4, -5 und -6 im Rahmen der „PlanAhead“ Software von Xilinx benutzt werden. DPR wird im Projekt im Sinne eines allgemeinen Coprozessors eingesetzt, indem die FPGA Konfiguration über die PCIe und die interne Konfigurationsschnittstelle („ICAP“) im FPGA nachgeladen wird. Um DPR bei hohen Taktgeschwindigkeiten einsetzen zu können, muss die Verbindungslogik zwischen den statischen und dynamischen Modulen speziellen Anforderungen genügen. Da die manuelle Anpassung existierenden Module an diese Anforderungen aufwändig und fehleranfällig ist, wurde das Programm „Logro“ entwickelt, das HDL Beschreibungen mittels einer speziellen Pipeline- Neustrukturierung automatisch so transformiert, dass die DPR Anforderungen erfüllt werden. Mit Logro V1.0 wurden dabei gute Ergebnisse erzielt, die hier vorgestellt werden

Implementing video compression algorithms on reconfigurable devices

The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder

Portable Waveform Development for Software Defined Radios

This work focuses on the question: "How can we build waveforms that can be moved from one platform to another?\u27\u27 Therefore an approach based on the Model Driven Architecture was evaluated. Furthermore, a proof of concept is given with the port of a TETRA waveform from a USRP platform to an SFF SDR platform

A novel parallel algorithm for surface editing and its FPGA implementation

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Doctor of PhilosophySurface modelling and editing is one of important subjects in computer graphics. Decades of research in computer graphics has been carried out on both low-level, hardware-related algorithms and high-level, abstract software. Success of computer graphics has been seen in many application areas, such as multimedia, visualisation, virtual reality and the Internet. However, the hardware realisation of OpenGL architecture based on FPGA (field programmable gate array) is beyond the scope of most of computer graphics researches. It is an uncultivated research area where the OpenGL pipeline, from hardware through the whole embedded system (ES) up to applications, is implemented in an FPGA chip. This research proposes a hybrid approach to investigating both software and hardware methods. It aims at bridging the gap between methods of software and hardware, and enhancing the overall performance for computer graphics. It consists of four parts, the construction of an FPGA-based ES, Mesa-OpenGL implementation for FPGA-based ESs, parallel processing, and a novel algorithm for surface modelling and editing. The FPGA-based ES is built up. In addition to the Nios II soft processor and DDR SDRAM memory, it consists of the LCD display device, frame buffers, video pipeline, and algorithm-specified module to support the graphics processing. Since there is no implementation of OpenGL ES available for FPGA-based ESs, a specific OpenGL implementation based on Mesa is carried out. Because of the limited FPGA resources, the implementation adopts the fixed-point arithmetic, which can offer faster computing and lower storage than the floating point arithmetic, and the accuracy satisfying the needs of 3D rendering. Moreover, the implementation includes Bézier-spline curve and surface algorithms to support surface modelling and editing. The pipelined parallelism and co-processors are used to accelerate graphics processing in this research. These two parallelism methods extend the traditional computation parallelism in fine-grained parallel tasks in the FPGA-base ESs. The novel algorithm for surface modelling and editing, called Progressive and Mixing Algorithm (PAMA), is proposed and implemented on FPGA-based ES’s. Compared with two main surface editing methods, subdivision and deformation, the PAMA can eliminate the large storage requirement and computing cost of intermediated processes. With four independent shape parameters, the PAMA can be used to model and edit freely the shape of an open or closed surface that keeps globally the zero-order geometric continuity. The PAMA can be applied independently not only FPGA-based ESs but also other platforms. With the parallel processing, small size, and low costs of computing, storage and power, the FPGA-based ES provides an effective hybrid solution to surface modelling and editing

Integrity Verification for SCADA Devices Using Bloom Filters and Deep Packet Inspection

In the past, SCADA networks were made secure through undocumented, proprietary protocols and isolation from other networks. Today, modern information technology (IT) solutions have provided a means to enhance remote access through use of the Internet. Unfortunately, opening SCADA networks to the Internet has provided routes of attack. Cyber attacks on these networks are becoming more common and can inflict considerable damage to critical infrastructure systems. Furthermore, devices on these networks can be infected with malware that causes them to falsify their responses to operators, concealing alternate operation or hiding alarm conditions. Considering their applications, securing these networks translates to improved physical security in the real world. Since modern IT solutions are impractical to deploy in the resource constrained SCADA networks, other solutions must be researched. This research evaluates an integrity verification system implemented on a Xilinx ML507 development board called the SIEVE system. The design incorporates Bloom filters and SCADA-specific intrusion detection techniques to speed identification of invalid commands and current sensing to investigate whether or not a device correctly carried out a given command. Results show that the SIEVE system is able to inspect and correctly identify 100% of network traffic at a 200 command per second frequency. Correct identification of valid MODBUS/TCP traffic begins to fail at 350 commands per second, introducing false positives. Tests of the Bloom filters show that they reduce the time necessary to process and log invalid MODBUS/TCP commands by 4.5% to 2328.06% depending on the number of operations performed by the command

Signal Processing for an Autonomous Underwater Vehicle: an FPGA approach

The idea of this thesis comes out from the participation of the University of Central Florida to the Annual International Autonomous Underwater Vehicle Competition of 2007. The objective of this competition is to make the AUV to accomplish to a specific route. A part of this route expects the AUV to detect a ping and following it as a source. The objective of this thesis is to improve the performance of this trajectory tracking. A Field Programmable Logic Array will be used to perform an effective Digital Signal Processing

Preliminary Electrical Designs for CTEx and AFIT Satellite Ground Station

This thesis outlines the design of the electrical components for the space-based ChromoTomography Experiment (CTEx). CTEx is the next step in the development of high-speed chromotomography at the Air Force Institute of Technology. The electrical design of the system is challenging due to the large amount of data that is acquired by the imager and the limited resources that is inherent with space-based systems. Additional complication to the design is the need to know the angle of a spinning prism that is in the field of view very precisely for each image. Without this precise measurement any scene that is reconstructed from the data will be blurry and incomprehensible. This thesis also outlines how the control software for the CTEx space system should be created. The software ow is a balance of complex real time target pointing angles and simplicity to allow the system to function as quick as possible. This thesis also discusses the preliminary design for an AFIT satellite ground station based upon the design of the United States Air Force Academy\u27s ground station. The AFIT ground station will be capable of commanding and controlling satellites produced by USAFA and satellites produced by a burgeoning small satellite program at AFIT