2,012 research outputs found
A jittered-sampling correction technique for ADCs
In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied
Analysis and application of digital spectral warping in analog and mixed-signal testing
Spectral warping is a digital signal processing transform which shifts the frequencies contained within a signal along the frequency axis. The Fourier transform coefficients of a warped signal correspond to frequency-domain 'samples' of the original signal which are unevenly spaced along the frequency axis. This property allows the technique to be efficiently used for DSP-based analog and mixed-signal testing. The analysis and application of spectral warping for test signal generation, response analysis, filter design, frequency response evaluation, etc. are discussed in this paper along with examples of the software and hardware implementation
Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters
The evaluation of the linearity performance of a high resolution Analog-to-
Digital Converter (ADC) by the Standard Histogram method is an outstanding
challenge due to the requirement of high purity of the input signal and
the high number of output data that must be acquired to obtain an acceptable
accuracy on the estimation. These requirements become major application
drawbacks when the measures have to be performed multiple times
within long test flows and for many parts, and under an industrial environment
that seeks to reduce costs and lead times as is the case in the New
Space sector. This thesis introduces two alternative methods that succeed
in relaxing the two previous requirements for the estimation of the Integral
Nonlinearity (INL) parameter in ADCs. The methods have been evaluated
by estimating the Integral Non-Linearity pattern by simulation using realistic
high-resolution ADC models and experimentally by applying them to real
high performance ADCs.
First, the challenge of applying the Standard Histogram method for the
evaluation of static parameters in high resolution ADCs and how the drawbacks
are accentuated in the New Space industry is analysed, being a highly
expensive method for an industrial environment where cost and lead time
reduction is demanded. Several alternative methods to the Standard Histogram
for estimating Integral Nonlinearity in high resolution ADCs are reviewed
and studied. As the number of existing works in the literature is very
large and addressing all of them is a challenge in itself, only those most relevant
to the development of this thesis have been included. Methods based
on spectral processing to reduce the number of data acquired for the linearity
test and methods based on a double histogram to be able to use generators
that do not meet the the purity requirement against the ADC to be tested are
further analysed.
Two novel contributions are presented in this work for the estimation of
the Integral Nonlinearity in ADCs, as possible alternatives to the Standard
Histogram method. The first method, referred to as SSA (Simple Spectral Approach),
seeks to reduce the number of output data that need to be acquired
and focuses on INL estimation using an algorithm based on processing the
spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard
Histogram method, although the estimation accuracy will depend on
how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm
cannot be used to perform a calibration of the ADC nonlinearity error,
but it can be applied to find out between which limits it lies and what its
approximate shape is. The second method, named SDH (Simplified Double
Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity
generator. The approach uses two histograms constructed from the
two set of output data in response to two identical input signals except for a
dc offset between them. Using a simple adder model, an extended approach
named ESDH (Extended Simplified Double Histogram) addresses and corrects
for possible time drifts during the two data acquisitions, so that it can
be successfully applied in a non-stationary test environment. According to
the experimental results obtained, the proposed algorithm achieves high estimation
accuracy.
Both contributions have been successfully tested in high-resolution ADCs
with both simulated and real laboratory experiments, the latter using a commercial
ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from
Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital
(ADC) de alta resolución mediante el método estándar del Histograma
constituye un gran desafío debido los requisitos de alta pureza de la señal
de entrada y del elevado número de datos de salida que deben adquirirse
para obtener una precisión aceptable en la estimación. Estos requisitos encuentran
importantes inconvenientes para su aplicación cuando las medidas
deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un
gran número de piezas, y todo bajo un entorno industrial que busca reducir
costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta
tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos
anteriores para la estimación de los parámetros de no linealidad en los
ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad
Integral (INL) mediante simulación utilizando modelos realistas de ADC de
alta resolución y experimentalmente aplicándolos en ADCs reales.
Inicialmente se analiza el reto que supone la aplicación del método estándar
del Histograma para la evaluación de los parámetros estáticos en ADCs
de alta resolución y cómo sus inconvenientes se acentúan en la industria del
Nuevo Espacio, siendo un método altamente costoso para un entorno industrial
donde se exige la reducción de costes y plazos de entrega. Se estudian
métodos alternativos al Histograma estándar para la estimación de la No Linealidad
Integral en ADCs de alta resolución. Como el número de trabajos es
muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos
más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número
de datos que necesitan ser adquiridos y los métodos basados en un doble
histograma para poder utilizar generadores que no cumplen el requisito de
precisión frente al ADC a medir.
En este trabajo se presentan dos novedosas aportaciones para la estimación
de la No Linealidad Integral en ADCs, como posibles alternativas al método
estándar del Histograma. El primer método, denominado SSA (Simple Spectral
Approach), busca reducir el número de datos de salida que es necesario
adquirir y se centra en la estimación de la INL mediante un algoritmo basado
en el procesamiento del espectro de la señal de salida cuando se utiliza un
estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número
mucho menor de muestras que el método estándar del Histograma, aunque
la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón
de no-linealidad del ADC a medir. En general, este algoritmo no puede
utilizarse para realizar una calibración del error de no linealidad del ADC,
pero puede aplicarse para averiguar entre qué límites se encuentra y cuál
es su forma aproximada. El segundo método, denominado SDH (Simplified
Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando
un generador de baja pureza. El algoritmo utiliza dos histogramas,
construidos a partir de dos conjuntos de datos de salida en respuesta a dos
señales de entrada idénticas, excepto por un desplazamiento constante entre
ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado
ESDH (Extended Simplified Double Histogram) aborda y corrige
las posibles derivas temporales durante las dos adquisiciones de datos, de
modo que puede aplicarse con éxito en un entorno de prueba no estacionario.
De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto
alcanza una alta precisión de estimación.
Ambas contribuciones han sido probadas en ADCs de alta resolución
con experimentos tanto simulados como reales en laboratorio, estos últimos
utilizando un ADC comercial con una resolución de 14 bits y una tasa de
muestreo de 65Msps (AD6644 de Analog Devices)
On-line health monitoring of passive electronic components using digitally controlled power converter
This thesis presents System Identification based On-Line Health Monitoring to analyse the dynamic behaviour of the Switch-Mode Power Converter (SMPC), detect, and diagnose anomalies in passive electronic components. The anomaly detection in this research is determined by examining the change in passive component values due to degradation. Degradation, which is a long-term process, however, is characterised by inserting different component values in the power converter. The novel health-monitoring capability enables accurate detection of passive electronic components despite component variations and uncertainties and is valid for different topologies of the switch-mode power converter.
The need for a novel on-line health-monitoring capability is driven by the need to improve unscheduled in-service, logistics, and engineering costs, including the requirement of Integrated Vehicle Health Management (IVHM) for electronic systems and components. The detection and diagnosis of degradations and failures within power converters is of great importance for aircraft electronic manufacturers, such as Thales, where component failures result in equipment downtime and large maintenance costs. The fact that existing techniques, including built-in-self test, use of dedicated sensors, physics-of-failure, and data-driven based health-monitoring, have yet to deliver extensive application in IVHM, provides the motivation for this research ... [cont.]
Hybrid receiver study
The results are presented of a 4 month study to design a hybrid analog/digital receiver for outer planet mission probe communication links. The scope of this study includes functional design of the receiver; comparisons between analog and digital processing; hardware tradeoffs for key components including frequency generators, A/D converters, and digital processors; development and simulation of the processing algorithms for acquisition, tracking, and demodulation; and detailed design of the receiver in order to determine its size, weight, power, reliability, and radiation hardness. In addition, an evaluation was made of the receiver's capabilities to perform accurate measurement of signal strength and frequency for radio science missions
Specific Heat of Liquid Helium in Zero Gravity very near the Lambda Point
We report the details and revised analysis of an experiment to measure the
specific heat of helium with subnanokelvin temperature resolution near the
lambda point. The measurements were made at the vapor pressure spanning the
region from 22 mK below the superfluid transition to 4 uK above. The experiment
was performed in earth orbit to reduce the rounding of the transition caused by
gravitationally induced pressure gradients on earth. Specific heat measurements
were made deep in the asymptotic region to within 2 nK of the transition. No
evidence of rounding was found to this resolution. The optimum value of the
critical exponent describing the specific heat singularity was found to be a =
-0.0127+ - 0.0003. This is bracketed by two recent estimates based on
renormalization group techniques, but is slightly outside the range of the
error of the most recent result. The ratio of the coefficients of the leading
order singularity on the two sides of the transition is A+/A- =1.053+ - 0.002,
which agrees well with a recent estimate. By combining the specific heat and
superfluid density exponents a test of the Josephson scaling relation can be
made. Excellent agreement is found based on high precision measurements of the
superfluid density made elsewhere. These results represent the most precise
tests of theoretical predictions for critical phenomena to date.Comment: 27 Pages, 20 Figure
System Identification, Diagnosis, and Built-In Self-Test of High Switching Frequency DC-DC Converters
abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby
accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum
load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
Breadboard linear array scan imager using LSI solid-state technology
The performance of large scale integration photodiode arrays in a linear array scan (pushbroom) breadboard was evaluated for application to multispectral remote sensing of the earth's resources. The technical approach, implementation, and test results of the program are described. Several self scanned linear array visible photodetector focal plane arrays were fabricated and evaluated in an optical bench configuration. A 1728-detector array operating in four bands (0.5 - 1.1 micrometer) was evaluated for noise, spectral response, dynamic range, crosstalk, MTF, noise equivalent irradiance, linearity, and image quality. Other results include image artifact data, temporal characteristics, radiometric accuracy, calibration experience, chip alignment, and array fabrication experience. Special studies and experimentation were included in long array fabrication and real-time image processing for low-cost ground stations, including the use of computer image processing. High quality images were produced and all objectives of the program were attained
A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS
Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR),
6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond.
This work proposes a robust, fault-tolerant scheme to achieve high SFDR in an av-
eraging flash A/D converter using comparator chopping. Chopping of comparators
in a flash A/D converter was never previously implemented due to lack of feasibility
in implementing multiple, uncorrelated, high speed random number generators. This
work proposes a novel array of uncorrelated truly binary random number generators
working at 1GHz to chop all comparators.
Chopping randomizes the residual offset left after averaging, further pushing
the dynamic range of the converter. This enables higher accuracy and lower bit-error
rate for high speed disk-drive read channels. Power consumption and area are reduced
because of the relaxed design requirements for the same linearity.
The technique has been verified in Matlab simulations for a 6-bit 1Gsamples/s
flash ADC under case of process gradients with non-zero mean offsets as high as 60mV
and potentially serious spot offset errors as high as 1V for a 2V peak to peak input
signal. The proposed technique exhibits an improvement of over 15dB compared to
pure averaging flash converters for all cases.
The circuit-level simulation results, for a 1V peak to peak input signal, demon-
strate superior performance. The reported ADC was fabricated in TSMC 0.18 ??mCMOS process. It occupies 8.79mm2 and consumes about 400mW from 1.8V power
supply at 1GHz. The targeted SFDR performance for the fabricated chip is at least
45dB for a 256MHz input sine wave, sampled at 1GHz, about 10dB improvement on
the 6-bit flash ADCs in the literature
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