40 research outputs found

    Enhanced Hardware Security Using Charge-Based Emerging Device Technology

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    The emergence of hardware Trojans has largely reshaped the traditional view that the hardware layer can be blindly trusted. Hardware Trojans, which are often in the form of maliciously inserted circuitry, may impact the original design by data leakage or circuit malfunction. Hardware counterfeiting and IP piracy are another two serious issues costing the US economy more than $200 billion annually. A large amount of research and experimentation has been carried out on the design of these primitives based on the currently prevailing CMOS technology. However, the security provided by these primitives comes at the cost of large overheads mostly in terms of area and power consumption. The development of emerging technologies provides hardware security researchers with opportunities to utilize some of the otherwise unusable properties of emerging technologies in security applications. In this dissertation, we will include the security consideration in the overall performance measurements to fully compare the emerging devices with CMOS technology. The first approach is to leverage two emerging devices (Silicon NanoWire and Graphene SymFET) for hardware security applications. Experimental results indicate that emerging device based solutions can provide high level circuit protection with relatively lower performance overhead compared to conventional CMOS counterpart. The second topic is to construct an energy-efficient DPA-resilient block cipher with ultra low-power Tunnel FET. Current-mode logic is adopted as a circuit-level solution to countermeasure differential power analysis attack, which is mostly used in the cryptographic system. The third investigation targets on potential security vulnerability of foundry insider\u27s attack. Split manufacturing is adopted for the protection on radio-frequency (RF) circuit design

    Miniaturized Transistors, Volume II

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    In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

    Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits

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    FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance and resistance extraction is crucial in the design and verification of Fin- FET integrated circuits. Though there are wide varieties of techniques available for parasitic extraction, FinFETs still pose tremendous challenges due to the complex geometries and user model of FinFETs. In this thesis, we propose three practical techniques for parasitic extraction of FinFET integrated circuits. The first technique we propose is to solve the dilemma that foundries and IP vendors face to protect the sensitive information which is prerequisite for accurate parasitic extraction. We propose an innovative solution to the challenge, by building a macro model around any region in 2D/3D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. The second technique we present is to reduce the truncation error introduced by the traditional Neumann boundary condition. We make a fundamental contribution to the theory of field solvers by proposing a class of absorbing boundary conditions, which when placed on the boundary of the numerical region, will act as if the region extends to infinity. As a result, we can significantly reduce the size of the numerical region, which in turn reduces the run time without sacrificing accuracy. Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM. The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example

    Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits

    Get PDF
    FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance and resistance extraction is crucial in the design and verification of Fin- FET integrated circuits. Though there are wide varieties of techniques available for parasitic extraction, FinFETs still pose tremendous challenges due to the complex geometries and user model of FinFETs. In this thesis, we propose three practical techniques for parasitic extraction of FinFET integrated circuits. The first technique we propose is to solve the dilemma that foundries and IP vendors face to protect the sensitive information which is prerequisite for accurate parasitic extraction. We propose an innovative solution to the challenge, by building a macro model around any region in 2D/3D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. The second technique we present is to reduce the truncation error introduced by the traditional Neumann boundary condition. We make a fundamental contribution to the theory of field solvers by proposing a class of absorbing boundary conditions, which when placed on the boundary of the numerical region, will act as if the region extends to infinity. As a result, we can significantly reduce the size of the numerical region, which in turn reduces the run time without sacrificing accuracy. Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM. The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example

    Journal of Telecommunications and Information Technology, 2007, nr 2

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    Miniaturized Transistors

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    What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

    Advances in Solid State Circuit Technologies

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    This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

    Radio Frequency InGaAs MOSFETs

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    III-V-based Indium gallium arsenide is a promising channel material for high-frequency applications due to its superior electron mobility property. In this thesis, InGaAs/InP heterostructure radio frequency MOSFETs are designed, fabricated, and characterized. Various spacer technologies, from high dielectric spacers to air spacers, are implemented to reduce parasitic capacitances, and fT/fmax are evaluated. Three types of RF MOSFETs with different spacer technologies are fabricated in this work.InP ∧-ridge spacers are integrated on InGaAs Nanowire MOSFET in an attempt to decrease parasitic capacitances; however, due to a high-dielectric constant of the spacers and smaller transistors transconductance, the fT/fmax are limited to 75/100 GHz. InGaAs quantum well MOSFETs with a sacrificial amorphous silicon spacer are fabricated, and they have capacitances of a similar magnitude to other existing high-performing RF InGaAs FETs. An 80 nm InGaAs MOSFET has fT/fmax = 243/147 GHz is demonstrated, and further optimization of the channel and layout would improve the performance. Next, InGaAs MOSFETs with nitride spacer are fabricated in a top-down approach, where the heterostructure is designed to reduce contact resistance and thus improve transconductance. In the first attempt, from the electrical characterization, it is concluded that the ON resistance of these MOSFETs is comparable to state-of-the-art HEMTs. Complete non-quasi-static small-signal modeling is performed on these transistors, and the discrepancy in the magnitude of fmax is discussed. InGaAs/InP 3D-nanosheet/nanowire FETs' high-frequency performance is studied by combining intrinsic analytical and extrinsic numerical models to estimate fT/fmax. 3D vertical stacking results in smaller parasitic capacitances due to electric field perturbance because of screening.An 8-band k⋅p model is implemented to calculate the electronic parameters of strained InxGa1-xAs/InP heterostructure-based quantum wells and nanowires. Bandgap, conduction band energy levels, and their effective masses and non-parabolicity factors are studied for various indium compositions and channel dimensions. These calculated parameters are used to model the long channel quantum well InGaAs MOSFET at cryogenic temperatures, and the importance of band tails limiting the subthreshold slope is discussed

    Compact Models for Integrated Circuit Design

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    This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

    III-V Nanowire MOSFET High-Frequency Technology Platform

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    This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems
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