Rtl Power Estimation of Sequential Circuits

Power consumption has become a major concern in the electronic industry in recent years because of the increased demand for portable electronic devices. Part of the problem in power conscious design is accurate power estimation. Power estimation at low-levels of design abstraction is slow since the units of low-levels of design abstraction are transistors or gates. But designers need reliable power estimates early in the design process. Therefore designers need to have tools for fast and accurate power estimation at higher levels of design abstraction such as the Register Transfer Level (RTL). This thesis introduces a new method for RTL power estimation of CMOS sequential circuits. This method tries to estimate the average power of a sequential circuit through the combination of a low-effort synthesis of the RTL description of the sequential circuit and the parameters readily available from the RTL description of the circuit like the sum-of-product count and literal count. The quantitative and qualitative aspects of the new model are studied with MCNC91 benchmark circuits and a large set of randomly generated circuits. Quantitative power estimation with the new model is seen to be very difficult because of the highly irregular surfaces of the functions that are being modeled in an effort to understand how a synthesis tool changes the power of a circuit during optimization. A qualitative measure is then proposed for the performance of a synthesis tool in preserving the qualitative ordering of power values of different implementations of a sequential circuit. An inference about such a performance of the synthesis tool would help the designer make informed decisions about the choice of implementation of a sequential circuit from a set of broad alternatives

Implementation Aspects of a Transmitted-Reference UWB Receiver

In this paper, we discuss the design issues of an ultra wide band (UWB) receiver targeting a single-chip CMOS implementation for low data-rate applications like ad hoc wireless sensor networks. A non-coherent transmitted reference (TR) receiver is chosen because of its small complexity compared to other architectures. After a brief recapitulation of the UWB fundamentals and a short discussion on the major differences between coherent and non-coherent receivers, we discuss issues, challenges and possible design solutions. Several simulation results obtained by means of a behavioral model are presented, together with an analysis of the trade-off between performance and complexity in an integrated circuit implementation

Statistical Estimation of Combinational and Sequential CMOS Digital Circuit Activity Considering Uncertainty of Gate Delay Models

While estimating glitches or spurious transitions is challenge due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more clifficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combini3tional and sequential CMOS logic circuits considering uncertainty of gate delay models. The methodology is based on the stochastic models of logic signals and the probabilistic behavior of gate delays due to process variations, interconnect parmitics, etc. We propose a statistical technique of estimating average-case activity, which is flexible in adopting different delay models and variations and can be integrated with worst-case analysis into statistical logic design process. Experimental results show that the uncertainty of gate delay makes a great impact on activity at individual nodes (more than 100%) and total power dissipation as well

Precomputation-based sequential logic optimization for low power

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 69-71).by Mazhar Murtaza Alidina.M.S

Compact Real-Time Inter-Frame Histogram Builder for 15-Bits High-Speed ToF-Imagers Based on Single-Photon Detection

Time-of-flight (ToF) image sensors based on single-photon detection, i.e., SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise, such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for the ToF computation. This method makes use of the shifted inter-frame histogram. It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 2 8 words memory is enough to process histograms containing up to 2 15 bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013European Union H2020 76586