Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

Investigation into yield and reliability enhancement of TSV-based three-dimensional integration circuits

Three dimensional integrated circuits (3D ICs) have been acknowledged as a promising technology to overcome the interconnect delay bottleneck brought by continuous CMOS scaling. Recent research shows that through-silicon-vias (TSVs), which act as vertical links between layers, pose yield and reliability challenges for 3D design. This thesis presents three original contributions.The first contribution presents a grouping-based technique to improve the yield of 3D ICs under manufacturing TSV defects, where regular and redundant TSVs are partitioned into groups. In each group, signals can select good TSVs using rerouting multiplexers avoiding defective TSVs. Grouping ratio (regular to redundant TSVs in one group) has an impact on yield and hardware overhead. Mathematical probabilistic models are presented for yield analysis under the influence of independent and clustering defect distributions. Simulation results using MATLAB show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratio results in achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios. The second contribution presents an efficient online fault tolerance technique based on redundant TSVs, to detect TSV manufacturing defects and address thermal-induced reliability issue. The proposed technique accounts for both fault detection and recovery in the presence of three TSV defects: voids, delamination between TSV and landing pad, and TSV short-to-substrate. Simulations using HSPICE and ModelSim are carried out to validate fault detection and recovery. Results show that regular and redundant TSVs can be divided into groups to minimise area overhead without affecting the fault tolerance capability of the technique. Synthesis results using 130-nm design library show that 100% repair capability can be achieved with low area overhead (4% for the best case). The last contribution proposes a technique with joint consideration of temperature mitigation and fault tolerance without introducing additional redundant TSVs. This is achieved by reusing spare TSVs that are frequently deployed for improving yield and reliability in 3D ICs. The proposed technique consists of two steps: TSV determination step, which is for achieving optimal partition between regular and spare TSVs into groups; The second step is TSV placement, where temperature mitigation is targeted while optimizing total wirelength and routing difference. Simulation results show that using the proposed technique, 100% repair capability is achieved across all (five) benchmarks with an average temperature reduction of 75.2? (34.1%) (best case is 99.8? (58.5%)), while increasing wirelength by a small amount

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Analog design for manufacturability: lithography-aware analog layout retargeting

As transistor sizes shrink over time in the advanced nanometer technologies, lithography effects have become a dominant contributor of integrated circuit (IC) yield degradation. Random manufacturing variations, such as photolithographic defect or spot defect, may cause fatal functional failures, while systematic process variations, such as dose fluctuation and defocus, can result in wafer pattern distortions and in turn ruin circuit performance. This dissertation is focused on yield optimization at the circuit design stage or so-called design for manufacturability (DFM) with respect to analog ICs, which has not yet been sufficiently addressed by traditional DFM solutions. On top of a graph-based analog layout retargeting framework, in this dissertation the photolithographic defects and lithography process variations are alleviated by geometrical layout manipulation operations including wire widening, wire shifting, process variation band (PV-band) shifting, and optical proximity correction (OPC). The ultimate objective of this research is to develop efficient algorithms and methodologies in order to achieve lithography-robust analog IC layout design without circuit performance degradation

Advanced Interior Point Formulation for the Global Routing Problem

As the circuit size increases in modern electronics, the design process becomes more complicated. Even though the hardware design process is divided into multiple phases, many of the divided problems are still extremely time consuming to solve. One of these NP-hard problems is the routing problem. As electronics step into the deep submicron era, optimizing the routing becomes increasingly important. One of the methods to solve global routing is to formulate the problem as an integer programming (IP) problem. This formulation can then be relaxed into a linear programming problem and solved using interior point method. This thesis investigates two new approaches to optimize the speed of solving global routing using Karmarkar’s interior point method, as well as the effect of combining various optimizations with these new approaches. The first proposed approach is to utilize solution stability as the interior point loop converges, and attempt to remove solutions that have already stabilized. This approach reduces the problem size and allows subsequent interior point iterations to proceed faster. The second proposed approach is to solve the inner linear system (projection step) in interior point method in parallel. Experimental results show that for large routing problems, the performance of the solver is improved by the optimization approaches. The problem reduction stage allows for great speedup in the interior point iterations, without affecting the quality of the solution significantly. Furthermore, the timing required to solve inner linear system in the interior point method is improved by solving the problem in parallel. With these optimizations, solving the routing problem using the IP formation becomes increasingly more efficient. By solving an efficient parallel IP formation rather than a traditional sequential approach, more efficient optimal solutions which incorporate multiple conflicting objectives can be achieved

New methods for the study of Primary Ciliary Dyskinesia

Os cilios e flagelos são projeções celulares encontradas nas células eucariotas, são altamente conservados entre espécies e envolvidos na locomoção e movimentação de fluídos. A Discinésia Ciliar Primária (DCP) é uma doenca genética autossómica recessiva dos cílios móveis, que tem como consequência várias manifestações clínicas. Estima-se que a DCP afete ~1 em cada 10.000 pessoas, mas é mais prevalente em grupos com marcada consanguinidade. A DCP está associada até à data a mais de 40 genes causadores de doença. O diagnóstico da DCP envolve a combinação de vários testes, entre eles a microscopia electrónica (ME), teste determinante na classificação de anomalias ciliares. Neste trabalho foquei-me nos cílios móveis e em como se classificam as derivações à estrutura considerada normal. Este estudo levou ao desenvolvimento de feramentas e diretrizes que tornam o diagnóstico de DCP por EM mais estandardizado, informativo e fidedigno. A DCP necessita de ser modelada em organismos vertebrados como o ratinho, a rã e o peixe-zebra (PZ) para melhor conhecimento dos seus mecanismos moleculares. O PZ é um bom modelo de DCP porque apresenta diversos órgãos ciliados durante os estados larvares (cílios moveis e imoveis) e tem, até agora, homólogos de todos os genes causadores da doença humana. Desta forma a utilização de peixes mutantes tem sido um bom contributo para compreender esta doença humana. Neste trabalho investiguei por ME dois tipos de cílios móveis do PZ concluindo que estes apresentam semelhanças estruturais conservadas com os cílios móveis das vias aéreas do ser humano saudável e com DCP.Cilia and flagella are cellular protrusions found in eucaryotic cells, highly conserved between species and found in almost every cell type. Motile cilia are known for their motility properties and are involved in propelling and moving fluids. Primary ciliary dyskinesia (PCD) is an inherited autosomal-recessive disorder of motile cilia that results in several clinical manifestations. The estimated prevalence of PCD is ∼1 per 10,000 births, but it is more prevalent in populations where consanguinity is common, it is currently associated with mutations in more than 40 genes. To diagnose PCD it involves a combination of tests, in particular, electron microscopy (EM) that is essential for determining the type of ciliary ultrastructural defect. In this work I have focused on motile cilia ultrastructure and how the differences in cilia can be identified and classified, through the development of tools and guidelines to make the quantification and analysis of cilia more reliable and informative. The differential diagnosis of PCD is complex but crucial, and the development of new potential targeted treatments is essential. For better investigating the molecular mechanisms underlying PCD, it has been modelled in several organisms like mice, frogs and Zebrafish (ZF). ZF is a teleost vertebrate used in many areas of research, and a well-known animal model. ZF embryos develop quickly and allow unique advantages for research studies owing to their transparency during larval stages. ZF has many ciliated organs and presents primary cilia as well as motile cilia together with homologs for all the disease causing genes. The use of mutant zebrafish has been contributing to the better understanding of PCD molecular aetiology. Here, I investigated whether zebrafish cilia are ultrastructurally suitable for the study of PCD and concluded that the motile cilia of zebrafish resemble the cilia in the human airway in healthy conditions and in PCD

From Field to Failure: Detecting and Understanding Reliability Defects in Crystalline Silicon Photovoltaics

Severe pollution levels and the growing influence of climate change have shown that dirty energy sources need renewable and sustainable replacements. The field of photovoltaics (PV) has grown substantially over the years from a niche space solar market to a commodity in large part due to improvements in reliability. Reliability of all materials in a PV module must be considered. The industry has seen an explosion of innovation in cell interconnection technologies with significant market penetration in the past several years. These emerging, less mature technologies require more reliability information to guide improvements. Degradation studies of long-term outdoor exposure and accelerated stress testing provide the samples, but a comprehensive characterization suite is necessary for impactful results. The state of the art for characterization is highly valuable yet incomplete. This work presents a multiscale, multicomponent process that provides information on device physics, polymer performance, thermal signatures, chemical composition, and degradation mechanisms, as well as advancements in electrical performance and defect localization. A comprehensive characterization suite is proposed which expands upon conventional one-sun current-voltage (I-V) and high injection electroluminescence (EL) imaging to multi-irradiance I-V, suns-Voc, multi-injection EL imaging and analysis, IR thermography, and UV fluorescence imaging. A database of over 1000 I-V curve, high-injection EL image pairs is presented for public use. An analysis and measurement technique is developed using EL images at multiple injection levels to non-destructively extract dark I-V curves for each cell. These curves can be analyzed to extract device properties. A machine learning model is developed using annotated EL images for automated defect detection. The training set of 17,064 cell EL images is publicized for the industry\u27s benefit. While applicable to all module technologies, the focus of this work is on applying this expansion on characterization to studying interconnection and contact degradation. Several interconnection technologies are studied with varying results. Each technology is shown to have distinct advantages and disadvantages with respect to performance and reliability. Modules are studied that have undergone accelerated tests and outdoor exposure. It is shown that full interconnection separation influences degradation differently depending on location of failure, though requires many failures before significant performance losses are evident. In another study, a model is developed for the mechanism behind front contact corrosion in damp heat degraded modules. A coring process is developed to extract cell samples which allows materials characterization. Results demonstrate that the primary mechanism is based on Sn diffusion from interconnection ribbons via acetic acid and moisture. One study examines a system of modules exposed in Florida for 10 years showing rear interconnect corrosion at the Ag/solder interface. Intermetallic compound formation led to reduced carrier transport and contact embrittlement leading to fatigue failure susceptibility. Another study investigates four different interconnection technologies before, during, and after stages of different accelerated stress protocols. Five-busbar ribbon, shingled, soldered wire, and laminated wire technologies underwent mechanical loading, humidity freeze, damp heat, and thermal cycling tests. Laminated wire performed the best overall though showed some features in EL imaging that have not yet been published. In the final study presented, a system of heterojunction modules from a system in Florida after 10 years exposure show resistive degradation. Device and materials characterization shows recombination and resistive losses, with resistive losses due corrosion at the intrinsic a-Si/c-Si interface