592 research outputs found
An Overview on Application of Machine Learning Techniques in Optical Networks
Today's telecommunication networks have become sources of enormous amounts of
widely heterogeneous data. This information can be retrieved from network
traffic traces, network alarms, signal quality indicators, users' behavioral
data, etc. Advanced mathematical tools are required to extract meaningful
information from these data and take decisions pertaining to the proper
functioning of the networks from the network-generated data. Among these
mathematical tools, Machine Learning (ML) is regarded as one of the most
promising methodological approaches to perform network-data analysis and enable
automated network self-configuration and fault management. The adoption of ML
techniques in the field of optical communication networks is motivated by the
unprecedented growth of network complexity faced by optical networks in the
last few years. Such complexity increase is due to the introduction of a huge
number of adjustable and interdependent system parameters (e.g., routing
configurations, modulation format, symbol rate, coding schemes, etc.) that are
enabled by the usage of coherent transmission/reception technologies, advanced
digital signal processing and compensation of nonlinear effects in optical
fiber propagation. In this paper we provide an overview of the application of
ML to optical communications and networking. We classify and survey relevant
literature dealing with the topic, and we also provide an introductory tutorial
on ML for researchers and practitioners interested in this field. Although a
good number of research papers have recently appeared, the application of ML to
optical networks is still in its infancy: to stimulate further work in this
area, we conclude the paper proposing new possible research directions
EARLY PERFORMANCE PREDICTION METHODOLOGY FOR MANY-CORES ON CHIP BASED APPLICATIONS
Modern high performance computing applications such as personal computing, gaming, numerical simulations require application-specific integrated circuits (ASICs) that comprises of many cores. Performance for these applications depends mainly on latency of interconnects which transfer data between cores that implement applications by distributing tasks. Time-to-market is a critical consideration while designing ASICs for these applications. Therefore, to reduce design cycle time, predicting system performance accurately at an early stage of design is essential. With process technology in nanometer era, physical phenomena such as crosstalk, reflection on the propagating signal have a direct impact on performance. Incorporating these effects provides a better performance estimate at an early stage. This work presents a methodology for better performance prediction at an early stage of design, achieved by mapping system specification to a circuit-level netlist description.
At system-level, to simplify description and for efficient simulation, SystemVerilog descriptions are employed. For modeling system performance at this abstraction, queueing theory based bounded queue models are applied. At the circuit level, behavioral Input/Output Buffer Information Specification (IBIS) models can be used for analyzing effects of these physical phenomena on on-chip signal integrity and hence performance.
For behavioral circuit-level performance simulation with IBIS models, a netlist must be described consisting of interacting cores and a communication link. Two new netlists, IBIS-ISS and IBIS-AMI-ISS are introduced for this purpose. The cores are represented by a macromodel automatically generated by a developed tool from IBIS models. The generated IBIS models are employed in the new netlists. Early performance prediction methodology maps a system specification to an instance of these netlists to provide a better performance estimate at an early stage of design. The methodology is scalable in nanometer process technology and can be reused in different designs
A Stub Equalizer for Bidirectional and Single-Ended Channels in NAND Memory Storage Device Systems
In memory devices, such as solid-state drive, multitopology is used for interfaces where multiple memory packages are connected to a controller using a branched transmission line. Impedance mismatching caused by the branches and unwanted reflection from deactivated packages inevitably degrades signal quality, limiting the data rate of the interface. In this article, a simple stub equalizer is proposed to improve the data rate of the memory interface. An open-ended stub is placed between a transmitter and a receiver, and the length, impedance, and location of the stub line are determined to properly cancel the reflection from other branches. Parameters are optimized based on the peak distortion analysis and an exhaustive search considering both read and write modes. The improvements are validated through eye-diagram simulations
Analysis and Design of High Speed Serial Interfaces for Automotive Applications
The demand for an enriched end-user experience and increased performance in next generation
electronic applications is never ending, and it is a common trend for a wide spectrum
of applications owing to different markets, like computing, mobile communication and automotive.
For this reason High Speed Serial Interface have become widespread components for
nowadays electronics with a constant demand for power reduction and data rate increase.
In the frame of gigabit serial systems, the work discussed in this thesis develops in two
directions: on one hand, the aim is to support the continuous data rate increase with the
development of novel link modeling approaches that will be employed for system level evaluation
and as support in the design and characterization phases. On the other hand, the
design considerations and challenges in the implementation of the transmitter, one of the
most delicate blocks for the signal integrity performance of the link, are central.
The first part of the activity regarding link performance predictions lead to the development
of an enhanced statistical simulation approach, capable to account for the transmitter
waveform shape in the ISI analysis, a characteristic that is missed by the available state-ofthe-
art simulation approaches. The proposed approach has been extensively tested by comparison
with traditional simulation approaches (Spice-like simulators) and validated against
experimental characterization of a test system, with satisfactory results.
The second part of the activity consists in the design of a high speed transmitter in a
deeply scaled CMOS technology, spanning from the concept of the circuit, its implementation
and characterization. Targets of the design are to achieve a data rate of 5 Gb/s with
a minimum voltage swing of 800 mV, thus doubling the data rate of the current transmitter
implementation, and reduce the power dissipation adopting a voltage mode architecture.
The experimental characterization of the fabricated lot draws a twofold picture, with some
of the performance figures showing a very good qualitative and quantitative agreement with
pre-silicon simulations, and others revealing a poor performance level, especially for the eye
diagram. Investigation of the root causes by the analysis of the physical silicon design, of the
bonding scheme of the prototypes and of the pre-silicon simulations is reported. Guidelines
for the redesign of the circuit are also given.Nel panorama delle applicazioni elettroniche il miglioramento delle performance di un prodotto
da una generazione alla successiva ha lo scopo di offrire all\u2019utilizzatore finale nuove
funzioni e migliorare quelle esistenti. Negli ultimi anni grazie al costante avanzamento della
tecnologia integrata, si \ue8 assistito ad un enorme sviluppo della capacit\ue0 computazionale dei
dispositivi in tutti i segmenti di mercato, quali ad esempio l\u2019information technology, la comunicazione
mobile e l\u2019automotive. La conseguente necessit\ue0 di mettere in comunicazione
dispostivi diversi all\u2019interno della stessa applicazione e di traferire grosse quantit\ue0 di dati ha
provocato una capillare diffusione delle interfacce seriali ad alta velocit\ue0, o High Speed Serial
Interfaces (HSSIs). La necessit\ue0 di ridurre il consumo di potenza e aumentare il bit rate per
questo tipo di applicazioni \ue8 diventata dunque un ambito di ricerca di estremo interesse.
Il lavoro discusso in questa tesi si colloca nell\u2019ambito della trasmissione di dati seriali a
bit rate superiori ad 1Gb/s e si sviluppa in due direzioni: da un lato, a sostegno del continuo
aumento del bit rate nelle nuove generazioni di interfacce, \ue8 stato affrontato lo sviluppo di
nuovi approcci di modellazione del sistema, che possano essere impiegati nella valutazione
delle prestazioni dell\u2019interfaccia e a supporto delle fasi di progettazione e di caratterizzazione.
Dall\u2019altro lato, si \ue8 focalizzata l\u2019attenzione sulle sfide e sulle problematiche inerenti il progetto
di uno dei blocchi pi\uf9 delicati per le prestazioni del sistema, il trasmettitore.
La prima parte della tesi ha come oggetto lo sviluppo di un approccio di simulazione
statistico innovativo, in grado di includere nell\u2019analisi degli effetti dell\u2019interferenza di intersimbolo
anche la forma d\u2019onda prodotta all\u2019uscita del trasmettitore, una caratteristica che
non \ue8 presente in altri approcci di simulazione proposti in letteratura. La tecnica proposta
\ue8 ampiamente testata mediante il confronto con approcci di simulazione tradizionali (di tipo
Spice) e mediante il confronto con la caratterizzazione sperimentale di un sistema di test, con
risultati pienamente soddisfacenti.
La seconda parte dell\u2019attivit\ue0 riguarda il progetto di un trasmettitore integrato high speed
in tecnologia CMOS a 40nm e si estende dallo studio di fattibilit\ue0 del circuito fino alla sua
realizzazione e caratterizzazione. Gli obiettivi riguardano il raggiungimento di un bit rate
pari a 5 Gb/s, raddoppiando cos\uec il bit rate dell\u2019attuale implementazione, e di una tensione
differenziale di uscita minima di 800mV (picco-picco) riducendo allo stesso tempo la potenza
dissipata mediante l\u2019adozione di una architettura Voltage Mode. I risultati sperimentali
ottenuti dal primo lotto fabbricato non delineano un quadro univoco: alcune performance
mostrano un ottimo accordo qualitativo e quantitativo con le simulazioni pre-fabbricazione,
mentre prestazioni non soddisfacenti sono state ottenute in particolare per il diagramma ad
occhio. Grazie all\u2019analisi del layout del prototipo, del bonding tra silicio e package e delle
simulazioni pre-fabbricazione \ue8 stato possibile risalire ai fattori responsabili del degrado delle
prestazioni rispetto alla previsioni pre-fabbricazione, permettendo inoltre di delineare le
linee guida da seguire nella futura progettazione di un nuovo prototipo
An investigation into the performance of a power-of-two coefficient transversal equalizer in a 34Mbit/s QPSK digital radio during frequency-selective fading conditions
Bibliography: leaves 82-91.Under certain atmospheric conditions, multipath propagation can occur. The interaction of radio waves arriving at a receiver, having travelled via paths of differing length, results in the phenomenon of frequency-selective fading. This phenomenon manifests as a notch in the received spectrum and causes a severe degradation in the performance of a digital radio system. As the total power in the received bandwidth may be unaffected, the Automatic Gain Control is not able to correct for this distortion, and so other methods are required. The dissertation commences with a summary of the phenomenon of multipath as this provides the context for the investigations which follow. The adaptive equalizer was developed to combat the distortion introduced by frequency-selective fading. It achieves this by applying an estimate of the inverse of the distorting channel's transfer function. The theory on adaptive equalizers has been well established, and a summary of this theory is presented in the form of Wiener Filter theory and the Wiener-Hopf equations. An adaptive equalizer located in a 34MBit/s QPSK digital radio is required to operate at very high speed, and its digital hardware implementation is not a trivial task. In order to reduce the cost and complexity, a compromise was proposed. If the tap weights of the equalizer could be represented by power-of-two binary numbers, the equalizer circuitry can be dramatically simplified. The aim of the dissertation was to investigate the performance of this simplified equalizer structure and to determine whether a power-of-two equalizer was a viable consideration
Stochastic Time-Domain Mapping for Comprehensive Uncertainty Assessment in Eye Diagrams
The eye diagram is one of the most common tools used for quality assessment in high-speed links. This article proposes a method of predicting the shape of the inner eye for a link subject to uncertainties. The approach relies on machine learning regression and is tested on the very challenging example of flexible link for smart textiles. Several sources of uncertainties are taken into account related to both manufacturing tolerances and physical deformation. The resulting model is fast and accurate. It is also extremely versatile: rather than focusing on a specific metric derived from the eye diagram, its aim is to fully reconstruct the inner eye and enable designers to use it as they see fit. This article investigates the features and convergence of three alternative machine learning algorithms, including the single-output support vector machine regression, together with its least squares variant, and the vector-valued kernel ridge regression. The latter method is arguably the most promising, resulting in an accurate, fast and robust tool enabling a complete parametric stochastic map of the eye
An Analytical Model for Performance Estimation in High-Capacity IMDD Systems
In this paper, we propose an analytical model to estimate the signal-to-noise
ratio (SNR) at the output of an adaptive equalizer in intensity modulation and
direct detection (IMDD) optical transmission systems affected by shot noise,
thermal noise, relative intensity noise (RIN), chromatic dispersion (CD) and
bandwidth limitations. We develop the model as an extension of a previously
presented one, and then we test its accuracy by sweeping the main parameters of
a 4-PAM-based communication system such as RIN coefficient, extinction ratio,
CD coefficient and equalizer memory. Our findings show a remarkable agreement
between time-domain simulations and analytical results, with SNR discrepancies
below 0.1 dB in most cases, for both feed-forward and decision-feedback
equalization. We consider that the proposed model is a powerful tool for the
numerical design of strongly band-limited IMDD systems using receiver
equalization, as it happens in most of modern and future M-PAM solutions for
short reach and access systems
Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications
The rapid proliferation of the Internet has been driving communication networks closer and closer to their limits, while available bandwidth is disappearing due to an ever-increasing network load. Over the past decade, optical fiber communication technology has increased per fiber data rate from 10 Tb/s to exceeding 10 Pb/s. The major explosion came after the maturity of coherent detection and advanced digital signal processing (DSP). DSP has played a critical role in accommodating channel impairments mitigation, enabling advanced modulation formats for spectral efficiency transmission and realizing flexible bandwidth. This book aims to explore novel, advanced DSP techniques to enable multi-Tb/s/channel optical transmission to address pressing bandwidth and power-efficiency demands. It provides state-of-the-art advances and future perspectives of DSP as well
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