Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy over Wide Frequency Ranges

Recently, there are increasing interests in impedance sensors for various applications. Direct digital synthesis (DDS) circuits are commonly used in such sensor circuits for generating stimulus signals, due to the advantages of accurate frequency control, drift-free performance, etc. Previously reported DDS circuits for sensor applications typically maintain superb frequency accuracy within relatively small frequency ranges. This paper investigates techniques to improve frequency accuracy over wide frequency ranges. In addition, it presents an analytical framework to estimate the signal to noise ratio (SNR) of the generated signal and derives guidelines for optimizing DDS circuit configurations. Both simulation and hardware measurement results are presented to validate the derived SNR estimation equation as well as the developed frequency accuracy enhancement technique

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd