62 research outputs found
Parameterized macromodeling of passive and active dynamical systems
L'abstract è presente nell'allegato / the abstract is in the attachmen
Nonlinear Black-Box Models of Digital Integrated Circuits via System Identification
This Thesis concerns the development of numerical macromodels of digi-
tal Integrated Circuits input/output buffers. Such models are of paramount
importance for the system-level simulation required for the assessment of Sig-
nal Integrity and Electromagnetic Compatibility effects in high-performance
electronic equipments via system-level simulations.
In order to obtain accurate and efficient macromodels, we concentrate on
the black-box modeling approach, exploiting system identification methods.
The present study contributes to the systematic discussion of the IC mod-
eling process, in order to obtain macromodels that can overcome strengths
and limitations of the methodologies presented so far. The performances of
different parametric representations, as Sigmoidal Basis Functions (SBF) ex-
pansions, Echo State Networks (ESN) and Local Linear State-Space (LLSS)
models are investigated. All representations have proven capabilities for the
modeling of unknown nonlinear dynamic systems and are good candidates too
be used for the modeling problem at hand. For each model representation,
the most suitable estimation algorithm is considered and a systematic analy-
sis is performed to highlight advantages and limitations. For this analysis,
the modeling process is applied to a synthetic nonlinear device representative
of IC ports, and designed to generate stiff responses.
The tests carried out show that LLSS models provide the best overall
performance for the modeling of digital devices, even with strong nonlinear
dynamics. LLSS models can be estimated by means of an efficient algorithm
providing a unique solution. Local stability of models is preconditioned and
verified a posteriori.
The effectiveness of the modeling process based on LLSS representations
is verified by applying the proposed technique to the modeling of real devices
involved in a realistic data communication link (an RF-to-Digital interface
used in mobile phones). The obtained macromodels have been successfully
used to predict both the functional signals and the power supply and ground
fluctuations. Besides, they turn out to be very efficient, providing a signifi-
cant simulation speed-up for the complete data link
Towards Enhancing Analog Circuits Sizing Using SMT-based Techniques
ABSTRACT This paper presents an approach for enhancing analog circuit sizing using Satisfiability Modulo Theory (SMT). The circuit sizing problem is encoded using nonlinear constraints. An SMT-based algorithm exhaustively explores the design space, where the biasing-level design variables are conservatively tracked using a collection of hyperrectangles. The device dimensions are then determined by accurately relating biasing to geometry-level design parameters. We demonstrate the feasibility and efficiency of the proposed methodology on a two-stage amplifier and a folded cascode amplifier. Experimental results show that our approach can achieve higher quality in analog synthesis and unrivaled coverage of the design space
Modeling, Optimization and Testing for Analog/Mixed-Signal Circuits in Deeply Scaled CMOS Technologies
As CMOS technologies move to sub-100nm regions, the design and verification
for analog/mixed-signal circuits become more and more difficult due to the problems
including the decrease of transconductance, severe gate leakage and profound mismatches.
The increasing manufacturing-induced process variations and their impacts
on circuit performances make the already complex circuit design even more sophisticated
in the deeply scaled CMOS technologies. Given these barriers, efforts are
needed to ensure the circuits are robust and optimized with consideration of parametric
variations. This research presents innovative computer-aided design approaches
to address three such problems: (1) large analog/mixed-signal performance modeling
under process variations, (2) yield-aware optimization for complex analog/mixedsignal
systems and (3) on-chip test scheme development to detect and compensate
parametric failures.
The first problem focus on the efficient circuit performance evaluation with consideration
of process variations which serves as the baseline for robust analog circuit
design. We propose statistical performance modeling methods for two popular
types of complex analog/mixed-signal circuits including Sigma-Delta ADCs and
charge-pump PLLs. A more general performance modeling is achieved by employing
a geostatistics motivated performance model (Kriging model), which is accurate
and efficient for capturing stand-alone analog circuit block performances. Based on the generated block-level performance models, we can solve the more challenging
problem of yield-aware system optimization for large analog/mixed-signal systems.
Multi-yield pareto fronts are utilized in the hierarchical optimization framework so
that the statistical optimal solutions can be achieved efficiently for the systems. We
further look into on-chip design-for-test (DFT) circuits in analog systems and solve
the problems of linearity test in ADCs and DFT scheme optimization in charge-pump
PLLs. Finally a design example of digital intensive PLL is presented to illustrate the
practical applications of the modeling, optimization and testing approaches for large
analog/mixed-signal systems
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Metamodeling-based Fast Optimization of Nanoscale Ams-socs
Modern consumer electronic systems are mostly based on analog and digital circuits and are designed as analog/mixed-signal systems on chip (AMS-SoCs). the integration of analog and digital circuits on the same die makes the system cost effective. in AMS-SoCs, analog and mixed-signal portions have not traditionally received much attention due to their complexity. As the fabrication technology advances, the simulation times for AMS-SoC circuits become more complex and take significant amounts of time. the time allocated for the circuit design and optimization creates a need to reduce the simulation time. the time constraints placed on designers are imposed by the ever-shortening time to market and non-recurrent cost of the chip. This dissertation proposes the use of a novel method, called metamodeling, and intelligent optimization algorithms to reduce the design time. Metamodel-based ultra-fast design flows are proposed and investigated. Metamodel creation is a one time process and relies on fast sampling through accurate parasitic-aware simulations. One of the targets of this dissertation is to minimize the sample size while retaining the accuracy of the model. in order to achieve this goal, different statistical sampling techniques are explored and applied to various AMS-SoC circuits. Also, different metamodel functions are explored for their accuracy and application to AMS-SoCs. Several different optimization algorithms are compared for global optimization accuracy and convergence. Three different AMS circuits, ring oscillator, inductor-capacitor voltage-controlled oscillator (LC-VCO) and phase locked loop (PLL) that are present in many AMS-SoC are used in this study for design flow application. Metamodels created in this dissertation provide accuracy with an error of less than 2% from the physical layout simulations. After optimal sampling investigation, metamodel functions and optimization algorithms are ranked in terms of speed and accuracy. Experimental results show that the proposed design flow provides roughly 5,000x speedup over conventional design flows. Thus, this dissertation greatly advances the state-of-the-art in mixed-signal design and will assist towards making consumer electronics cheaper and affordable
Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits
The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated.
For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework.
In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Fathianathan, Mervyn; Committee Member: Lim, Sung Kyu; Committee Member: Peterson, Andrew; Committee Member: Tentzeris, Mano
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
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