Adaptive design of delta sigma modulators

In this thesis, a genetic algorithm based on differential evolution (DE) is used to generate delta sigma modulator (DSM) noise transfer functions (NTFs). These NTFs outperform those generated by an iterative approach described by Schreier and implemented in the delsig Matlab toolbox. Several lowpass and bandpass DSMs, as well as DSM\u27s designed specifically for and very low intermediate frequency (VLIF) receivers are designed using the algorithm developed in this thesis and compared to designs made using the delsig toolbox. The NTFs designed using the DE algorithm always have a higher dynamic range and signal to noise ratio than those designed using the delsig toolbox

Design of a reusable distributed arithmetic filter and its application to the affine projection algorithm

Digital signal processing (DSP) is widely used in many applications spanning the spectrum from audio processing to image and video processing to radar and sonar processing. At the core of digital signal processing applications is the digital filter which are implemented in two ways, using either finite impulse response (FIR) filters or infinite impulse response (IIR) filters. The primary difference between FIR and IIR is that for FIR filters, the output is dependent only on the inputs, while for IIR filters the output is dependent on the inputs and the previous outputs. FIR filters also do not sur from stability issues stemming from the feedback of the output to the input that aect IIR filters. In this thesis, an architecture for FIR filtering based on distributed arithmetic is presented. The proposed architecture has the ability to implement large FIR filters using minimal hardware and at the same time is able to complete the FIR filtering operation in minimal amount of time and delay when compared to typical FIR filter implementations. The proposed architecture is then used to implement the fast affine projection adaptive algorithm, an algorithm that is typically used with large filter sizes. The fast affine projection algorithm has a high computational burden that limits the throughput, which in turn restricts the number of applications. However, using the proposed FIR filtering architecture, the limitations on throughput are removed. The implementation of the fast affine projection adaptive algorithm using distributed arithmetic is unique to this thesis. The constructed adaptive filter shares all the benefits of the proposed FIR filter: low hardware requirements, high speed, and minimal delay.Ph.D.Committee Chair: Anderson, Dr. David V.; Committee Member: Hasler, Dr. Paul E.; Committee Member: Mooney, Dr. Vincent J.; Committee Member: Taylor, Dr. David G.; Committee Member: Vuduc, Dr. Richar

Hybrid DDS-PLL based reconfigurable oscillators with high spectral purity for cognitive radio

Analytical, design and simulation studies on the performance optimization of reconfigurable architecture of a Hybrid DDS – PLL are presented in this thesis. The original contributions of this thesis are aimed towards the DDS, the dithering (spur suppression) scheme and the PLL. A new design of Taylor series-based DDS that reduces the dynamic power and number of multipliers is a significant contribution of this thesis. This thesis compares dynamic power and SFDR achieved in the design of varieties of DDS such as Quartic, Cubic, Linear and LHSC. This thesis proposes two novel schemes namely “Hartley Image Suppression” and “Adaptive Sinusoidal Interference Cancellation” overcoming the low noise floor of traditional dithering schemes. The simulation studies on a Taylor series-based DDS reveal an improvement in SFDR from 74 dB to 114 dB by using Least Mean Squares -Sinusoidal Interference Canceller (LM-SIC) with the noise floor maintained at -200 dB. Analytical formulations have been developed for a second order PLL to relate the phase noise to settling time and Phase Margin (PM) as well as to relate jitter variance and PM. New expressions relating phase noise to PM and lock time to PM are derived. This thesis derives the analytical relationship between the roots of the characteristic equation of a third order PLL and its performance metrics like PM, Gardner’s stability factor, jitter variance, spur gain and ratio of noise power to carrier power. This thesis presents an analysis to relate spur gain and capacitance ratio of a third order PLL. This thesis presents an analytical relationship between the lock time and the roots of its characteristic equation of a third order PLL. Through Vieta’s circle and Vieta’s angle, the performance metrics of a third order PLL are related to the real roots of its characteristic equation

Signal processing methodologies for an acoustic fetal heart rate monitor

Research and development is presented of real time signal processing methodologies for the detection of fetal heart tones within a noise-contaminated signal from a passive acoustic sensor. A linear predictor algorithm is utilized for detection of the heart tone event and additional processing derives heart rate. The linear predictor is adaptively 'trained' in a least mean square error sense on generic fetal heart tones recorded from patients. A real time monitor system is described which outputs to a strip chart recorder for plotting the time history of the fetal heart rate. The system is validated in the context of the fetal nonstress test. Comparisons are made with ultrasonic nonstress tests on a series of patients. Comparative data provides favorable indications of the feasibility of the acoustic monitor for clinical use

The design and implementation of a microprocessor controlled adaptive filter

This thesis describes the construction and implementation of a microprocessor controlled recursive adaptive filter applied as a noise canceller. It describes the concept of the adaptive noise canceller, a method of estimating the received signal corrupted with additive interference (noise). This canceller has two inputs, the primary input containing the corrupted signal and the reference input consisting of the additive noise correlated in some unknown way to the primary noise. The reference input is filtered and subtracted from the primary input without degrading the desired components of the signal. This filtering process is adaptive and based on Widrow-Hoff Least-Mean-Square algorithm. Adaptive filters are programmable and have the capability to adjust their own parameters in situations where minimum piori knowledge is available about the inputs. For recursive filters, these parameters include feed-forward (non-recursive) as well as feedback (recursive) coefficients. A new design and implementation of the adaptive filter is suggested which uses a high speed 68000 microprocessor to accomplish the coefficients updating operation. Many practical problems arising in the hardware implementation are investigated. Simulation results illustrate the ability of the adaptive noise canceller to have an acceptable performance when the coefficients updating operation is carried out once every N sampling periods. Both simulation and hardware experimental results are in agreement

Itseishäiriön Kumoajan Digitaalinen Ohjaus

In traditional wireless communication systems, transmission and reception are divided in either time or frequency domain. In-band full-duplex means that the transmission and reception take place on the same frequency simultaneously, theoretically doubling the spectral efficiency. The most significant challenge in wireless full-duplex communication is the self-interference, which causes the systems own transmission signal to be coupled into the receiver. An analog canceller is designed to remove this self-interference from the reception signal. The cancellation takes place entirely in the RF domain. Any variation in the surroundings of the antenna also affect the self-interference. A control system is required to track these changes and adjust the canceller accordingly. This thesis presents a digital control system for the canceller. The control system is implemented using a field-programmable gate array (FPGA). The canceller and the control system were developed at Tampere University of Technology (TUT) in collaboration with Intel Labs. The project was concluded in January 2016, when the finished setup was delivered to Intel Labs. Using the digital control system, the canceller is capable of canceling up to 68 dB, 66 dB and 63 dB of the self-interference from the reception signal with 20 MHz, 40 MHz and 80 MHz signal bandwidths respectively. Roughly 20 dB of the cancellation originates from the intrinsic attenuation between the transmitter and the receiver. The control system is also capable of reacting and adapting to any changes in the self-interference quickly in order to maintain sufficient cancellation in a dynamic environment

An FPGA architecture design of a high performance adaptive notch filter

The occurrence of narrowband interference near frequencies carrying information is a common problem in modern control and signal processing applications. A very narrow notch filter is required in order to remove the unwanted signal while not compromising the integrity of the carrier signal. In many practical situations, the interference may wander within a frequency band, in which case a wider notch filter would be needed to guarantee its removal, which may also allow for the degradation of information being carried in nearby frequencies. If the interference frequency could be autonomously tracked, a narrow bandwidth notch filter could be successfully implemented for the particular frequency. Adaptive signal processing is a powerful technique that can be used in the tracking and elimination of such a signal. An application where an adaptive notch filter becomes necessary is in biomedical instrumentation, such as the electrocardiogram recorder. The recordings can become useless when in the presence of electromagnetic fields generated by power lines. Research was conducted to fully characterize the interference. Research on notch filter structures and adaptive filter algorithms has been carried out. The lattice form filter structure was chosen for its inherent stability and performance benefits. A new adaptive filter algorithm was developed targeting a hardware implementation. The algorithm used techniques from several other algorithms that were found to be beneficial. This work developed the hardware implementation of a lattice form adaptive notch filter to be used for the removal of power line interference from electrocardiogram signals. The various design tradeo s encountered were documented. The final design was targeted toward multiple field programmable gate arrays using multiple optimization efforts. Those results were then compared. The adaptive notch filter was able to successfully track and remove the interfering signal. The lattice form structure utilized by the proposed filter was verified to exhibit an inherently stable realization. The filter was subjected to various environments that modeled the different power line disturbances that could be present. The final filter design resulted in a 3 dB bandwidth of 15.8908 Hz, and a null depth of 54 dB. For the baseline test case, the algorithm achieved convergence after 270 iterations. The final hardware implementation was successfully verified against the MATLAB simulation results. A speedup of 3.8 was seen between the Xilinx Virtex-5 and Spartan-II device technologies. The final design used a small fraction of the available resources for each of the two devices that were characterized. This would allow the component to be more readily available to be added to existing projects, or further optimized by utilizing additional logic

IMPLEMENTATION OF NOISE CANCELLATION WITH HARDWARE DESCRIPTION LANGUAGE

The objective of this project is to implement noise cancellation technique on an FPGA using Hardware Description Language. The performance of several adaptive algorithms is compared to determine the desirable algorithm used for adaptive noise cancellation system. The project will focus on the implementation of adaptive filter with least-meansquares (LMS) algorithm or normalized least-mean-squares (NLMS) algorithm to cancel acoustic noises. This noise consists of extraneous or unwanted waveforms that can interfere with communication. Due to the simplicity and effectiveness of adaptive noise cancellation technique, it is used to remove the noise component from the desired signal. The project is divided into four main parts: research, Matlab simulation, ModelSim simulation and hardware implementation. The project starts with research on several noise cancellation techniques, and then with Matlab code, Simulink and FDA tool, the adaptive noise cancellation system is designed with the implementation of the LMS algorithm, NLMS algorithm and recursive-least-square algorithm to remove the interference noise. By using the Matlab code and Simulink, the noise that interfered with a sinusoidal signal and a record of music can be removed. The original signal in turns can be retrieved from the noise corrupted signal by changing the coefficient of the filter. Since filter is the important component in adaptive filtering process, the filter is designed first before adding adaptive algorithm. A Finite Impulse Response (FIR) filter is designed and the desired result of functional simulation and timing simulation is obtained through ModelSim and Integrated Software Environment (ISE) software and FPGA implementation. Finally the adaptive algorithm is added to the filter, and implemented in the FPGA. The noise is greatly reduced in Matlab simulation, functional simulation and timing simulation. Hence the results of this project show that noise cancellation with adaptive filter is feasible