A Study on the Noise Threshold of Fault-tolerant Quantum Error Correction

Quantum circuits implementing fault-tolerant quantum error correction (QEC) for the three qubit bit-flip code and five-qubit code are studied. To describe the effect of noise, we apply a model based on a generalized effective Hamiltonian where the system-environment interactions are taken into account by including stochastic fluctuating terms in the system Hamiltonian. This noise model enables us to investigate the effect of noise in quantum circuits under realistic device conditions and avoid strong assumptions such as maximal parallelism and weak storage errors. Noise thresholds of the QEC codes are calculated. In addition, the effects of imprecision in projective measurements, collective bath, fault-tolerant repetition protocols, and level of parallelism in circuit constructions on the threshold values are also studied with emphasis on determining the optimal design for the fault-tolerant QEC circuit. These results provide insights into the fault-tolerant QEC process as well as useful information for designing the optimal fault-tolerant QEC circuit for particular physical implementation of quantum computer.Comment: 9 pages, 9 figures; to be submitted to Phys. Rev.

Investigation of the applicability of a functional programming model to fault-tolerant parallel processing for knowledge-based systems

In a fault-tolerant parallel computer, a functional programming model can facilitate distributed checkpointing, error recovery, load balancing, and graceful degradation. Such a model has been implemented on the Draper Fault-Tolerant Parallel Processor (FTPP). When used in conjunction with the FTPP's fault detection and masking capabilities, this implementation results in a graceful degradation of system performance after faults. Three graceful degradation algorithms have been implemented and are presented. A user interface has been implemented which requires minimal cognitive overhead by the application programmer, masking such complexities as the system's redundancy, distributed nature, variable complement of processing resources, load balancing, fault occurrence and recovery. This user interface is described and its use demonstrated. The applicability of the functional programming style to the Activation Framework, a paradigm for intelligent systems, is then briefly described

An aircraft sensor fault tolerant system

The design of a sensor fault tolerant system which uses analytical redundancy for the Terminal Configured Vehicle (TCV) research aircraft in a Microwave Landing System (MLS) environment was studied. The fault tolerant system provides reliable estimates for aircraft position, velocity, and attitude in the presence of possible failures in navigation aid instruments and onboard sensors. The estimates, provided by the fault tolerant system, are used by the automated guidance and control system to land the aircraft along a prescribed path. Sensor failures are identified by utilizing the analytic relationship between the various sensor outputs arising from the aircraft equations of motion

Complex Patterns of Failure:Fault Tolerance via Complex Event Processing for IoT Systems

Fault-tolerance (FT) support is a key challenge for ensuring dependable Internet of Things (IoT) systems. Many existing FT-support mechanisms for IoT are static, tightly coupled, and inflexible, and so they struggle to provide effective support for dynamic IoT environments. This paper proposes Complex Patterns of Failure (CPoF), an approach to providing FT support for IoT systems using Complex Event Processing (CEP) that promotes modularity and reusability in FT-support design. System defects are defined using our Vulnerabilities, Faults, and Failures (VFF) framework, and error-detection strategies are defined as nondeterministic finite automata (NFA) implemented via CEP systems. We evaluated CPoF on an automated agriculture system and demonstrated its effectiveness against three types of error-detection checks: reasonableness, timing, and reversal. Using CPoF, we identified unreasonable environmental conditions and performance degradation via sensor data analysis

Software safety : a definition and some preliminary thoughts

Software safety is the subject of a research project in its initial stages at the University of California Irvine. This research deals with critical real-time software where the cost of an error is high, e.g. human life. In this paper software techniques having a bearing on safety are described and evaluated. Initial definitions of software safety concepts are presented along with some preliminary thoughts and research questions

Airborne Advanced Reconfigurable Computer System (ARCS)

A digital computer subsystem fault-tolerant concept was defined, and the potential benefits and costs of such a subsystem were assessed when used as the central element of a new transport's flight control system. The derived advanced reconfigurable computer system (ARCS) is a triple-redundant computer subsystem that automatically reconfigures, under multiple fault conditions, from triplex to duplex to simplex operation, with redundancy recovery if the fault condition is transient. The study included criteria development covering factors at the aircraft's operation level that would influence the design of a fault-tolerant system for commercial airline use. A new reliability analysis tool was developed for evaluating redundant, fault-tolerant system availability and survivability; and a stringent digital system software design methodology was used to achieve design/implementation visibility

A project to investigate mechanisms and methodologies for the design and construction of communicating concurrent processes in real-time environments

Research undertaken in 1979 into effective and appropriate mechanisms to aid in the design and construction of software for use in the flight research programs undertaken by NASA is presented

Efficient memory management in video on demand servers

In this article we present, analyse and evaluate a new memory management technique for video-on-demand servers. Our proposal, Memory Reservation Per Storage Device (MRPSD), relies on the allocation of a fixed, small number of memory buffers per storage device. Selecting adequate scheduling algorithms, information storage strategies and admission control mechanisms, we demonstrate that MRPSD is suited for the deterministic service of variable bit rate streams to intolerant clients. MRPSD allows large memory savings compared to traditional memory management techniques, based on the allocation of a certain amount of memory per client served, without a significant performance penaltyPublicad