85 research outputs found
Pre-validation of SoC via hardware and software co-simulation
Abstract. System-on-chips (SoCs) are complex entities consisting of multiple hardware and software components. This complexity presents challenges in their design, verification, and validation. Traditional verification processes often test hardware models in isolation until late in the development cycle. As a result, cooperation between hardware and software development is also limited, slowing down bug detection and fixing.
This thesis aims to develop, implement, and evaluate a co-simulation-based pre-validation methodology to address these challenges. The approach allows for the early integration of hardware and software, serving as a natural intermediate step between traditional hardware model verification and full system validation. The co-simulation employs a QEMU CPU emulator linked to a register-transfer level (RTL) hardware model. This setup enables the execution of software components, such as device drivers, on the target instruction set architecture (ISA) alongside cycle-accurate RTL hardware models.
The thesis focuses on two primary applications of co-simulation. Firstly, it allows software unit tests to be run in conjunction with hardware models, facilitating early communication between device drivers, low-level software, and hardware components. Secondly, it offers an environment for using software in functional hardware verification.
A significant advantage of this approach is the early detection of integration errors. Software unit tests can be executed at the IP block level with actual hardware models, a task previously only possible with costly system-level prototypes. This enables earlier collaboration between software and hardware development teams and smoothens the transition to traditional system-level validation techniques.Järjestelmäpiirin esivalidointi laitteiston ja ohjelmiston yhteissimulaatiolla. Tiivistelmä. Järjestelmäpiirit (SoC) ovat monimutkaisia kokonaisuuksia, jotka koostuvat useista laitteisto- ja ohjelmistokomponenteista. Tämä monimutkaisuus asettaa haasteita niiden suunnittelulle, varmennukselle ja validoinnille. Perinteiset varmennusprosessit testaavat usein laitteistomalleja eristyksissä kehityssyklin loppuvaiheeseen saakka. Tämän myötä myös yhteistyö laitteisto- ja ohjelmistokehityksen välillä on vähäistä, mikä hidastaa virheiden tunnistamista ja korjausta.
Tämän diplomityön tavoitteena on kehittää, toteuttaa ja arvioida laitteisto-ohjelmisto-yhteissimulointiin perustuva esivalidointimenetelmä näiden haasteiden ratkaisemiseksi. Menetelmä mahdollistaa laitteiston ja ohjelmiston varhaisen integroinnin, toimien luonnollisena välietappina perinteisen laitteistomallin varmennuksen ja koko järjestelmän validoinnin välillä. Yhteissimulointi käyttää QEMU suoritinemulaattoria, joka on yhdistetty rekisterinsiirtotason (RTL) laitteistomalliin. Tämä mahdollistaa ohjelmistokomponenttien, kuten laiteajureiden, suorittamisen kohdejärjestelmän käskysarja-arkkitehtuurilla (ISA) yhdessä kellosyklitarkkojen RTL laitteistomallien kanssa.
Työ keskittyy kahteen yhteissimulaation pääsovellukseen. Ensinnäkin se mahdollistaa ohjelmiston yksikkötestien suorittamisen laitteistomallien kanssa, varmistaen kommunikaation laiteajurien, matalan tason ohjelmiston ja laitteistokomponenttien välillä. Toiseksi se tarjoaa ympäristön ohjelmiston käyttämiseen toiminnallisessa laitteiston varmennuksessa.
Merkittävä etu tästä lähestymistavasta on integraatiovirheiden varhainen havaitseminen. Ohjelmiston yksikkötestejä voidaan suorittaa jo IP-lohkon tasolla oikeilla laitteistomalleilla, mikä on aiemmin ollut mahdollista vain kalliilla järjestelmätason prototyypeillä. Tämä mahdollistaa aikaisemman ohjelmisto- ja laitteistokehitystiimien välisen yhteistyön ja helpottaa siirtymistä perinteisiin järjestelmätason validointimenetelmiin
OVM compliant verification for a wishbone compatible i2c master controller core
Increasing design complexity and concurrency of Integrated Circuits has made traditional directed testbenches an unworkable solution for testing. Today, testing as a word has been substituted with verification. Verification engineers have to ensure what goes to the factory for manufacturing is an accurate representation of the design specification. Inter Integrated Circuit (I2C) bus is a very widely used communication protocol in embedded system design due to its hardware simplicity and high data transfer rates capability. Most ICs incorporate I2C interface. Thus the ASIC design process of these ICs calls for robust, independent and exhaustive verification to reduce the risks of their failures. Open Verification Methodology (OVM) is an open source verification methodology library intended to run on multiple platforms and be supported by multiple EDA vendors. This thesis attempts to study and hence introduces a comprehensive verification environment for the latest specifications of the I2C bus protocol realized in the OVM platform, a new industry standard for comprehensive verification due to its rich base classes and OOP features. This work has been challenging since very few work has been reported in this domain for reference
Improving Reusability in SoC Project Verification Flow
This main target of the thesis is to increase the level of reuse done in SoC verification projects. The verification takes the biggest amount of time in the project duration. This thesis contains 3 main parts. The first one introduces the reuse in SoC and explains its different dimensions as a literature study. This work is done as a background for the next two phases.
During the second part of this work, a practical example for verification reuse was implemented as a part of a SoC project. The reuse was applied vertically, where an IP-level testbench was altered to become reusable, then it was reused in a subsystem-level testbench. Additionally, analysis was done in order to know how much effort was reused in the project. Results show that 85% of the code was saved when the reuse was applied.
Regarding the third part of the thesis, several interviews were conducted with SoC verification experts who work at Nokia with a range of experience in the field from 7 to 20 years. These interviews were done in order to collect some information about how to improve the reusability in SoC project verification flow. The point from these interviews is to get knowledge from hands-on-experience. The interviewees agreed on the importance for applying the reuse in every verification project from the beginning of the project. They also agreed on maintaining the hierarchical level of reuse, which means IP-level TB would be a sub-environment of subsystem-level TB and subsystem-level is a sub-environment of SoC-level TB. Moreover, some ideas about the future work are introduced here. Those are proposed according to the knowledge gained from the research and from the interviews with the experts
Continuous Integration for Fast SoC Algorithm Development
Digital systems have become advanced, hard to design and optimize due to ever-growing technology. Integrated Circuits (ICs) have become more complicated due to complex computations in latest technologies. Communication systems such as mobile networks have evolved and become a part of our daily lives with the advancement in technology over the years. Hence, need of efficient, reusable and automated processes for System-on-a-Chip (SoC) development has been increased. Purpose of this thesis is to study and evaluate currently used SoC development processes and presents guidelines on how these processes can be streamlined.
The thesis starts by evaluating currently used SoC development flows and their advantages and disadvantages. One important aspect is to identify step which cause duplication of work and unnecessary idle times in SoC development teams. A study is conducted and input from SoC development experts is taken in order to optimize SoC flows and use of Continuous Integration (CI) system. An algorithm model is implemented that can be used in multiple stages of SoC development at adequate complexity and is “easy enough” to be used for a person not mastering the topic. The thesis outcome is proposal for CI system in SoC development for accelerating the speed and reliability of implementing algorithms to RTL code and finally into product. CI system tool is also implemented to automate and test the model design so that it also remains up to date
Tydi-lang: A Language for Typed Streaming Hardware
Transferring composite data structures with variable-length fields often
requires designing non-trivial protocols that are not compatible between
hardware designs. When each project designs its own data format and protocols
the ability to collaborate between hardware developers is diminished, which is
an issue especially in the open-source community. Because the high-level
meaning of a protocol is often lost in translation to low-level languages when
a custom protocol needs to be designed, extra documentation is required, the
interpretation of which introduces new opportunities for errors.
The Tydi specification (Tydi-spec) was proposed to address the above issues
by codifying the composite and variable-length data structures in a type and
providing a standard protocol to transfer typed data among hardware components.
The Tydi intermediate representation (Tydi-IR) extends the Tydi-spec by
defining typed interfaces, typed components, and connections among typed
components.
In this paper, we propose Tydi-lang, a high-level hardware description
language (HDL) for streaming designs. The language incorporates Tydi-spec to
describe typed streams and provides templates to describe abstract reusable
components. We also implement an open-source compiler from Tydi-lang to
Tydi-IR. We leverage a Tydi-IR to VHDL compiler, and also present a simulator
blueprint to identify streaming bottlenecks. We show several Tydi-lang examples
to translate high-level SQL to VHDL to demonstrate that Tydi-lang can
efficiently raise the level of abstraction and reduce design effort.Comment: 8 pages and 1 page of reference, 4 figures, 4 table
VeriSFQ - A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology
In this paper, we propose a semi-formal verification framework for
single-flux quantum (SFQ) circuits called VeriSFQ, using the Universal
Verification Methodology (UVM) standard. The considered SFQ technology is
superconducting digital electronic devices that operate at cryogenic
temperatures with active circuit elements called the Josephson junction, which
operate at high switching speeds and low switching energy - allowing SFQ
circuits to operate at frequencies over 300 gigahertz. Due to key differences
between SFQ and CMOS logic, verification techniques for the former are not as
advanced as the latter. Thus, it is crucial to develop efficient verification
techniques as the complexity of SFQ circuits scales. The VeriSFQ framework
focuses on verifying the key circuit and gate-level properties of SFQ logic:
fanout, gate-level pipeline, path balancing, and input-to-output latency. The
combinational circuits considered in analyzing the performance of VeriSFQ are:
Kogge-Stone adders (KSA), array multipliers, integer dividers, and select
ISCAS'85 combinational benchmark circuits. Methods of introducing bugs into SFQ
circuit designs for verification detection were experimented with - including
stuck-at faults, fanout errors, unbalanced paths, and functional bugs like
incorrect logic gates. In addition, we propose an SFQ verification benchmark
consisting of combinational SFQ circuits that exemplify SFQ logic properties
and present the performance of the VeriSFQ framework on these benchmark
circuits. The portability and reusability of the UVM standard allows the
VeriSFQ framework to serve as a foundation for future SFQ semi-formal
verification techniques.Comment: 7 pages, 6 figures, 4 tables; submitted, accepted, and presented at
ISQED 2019 (20th International Symposium on Quality Electronic Design) on
March 7th, 2019 in Santa Clara, CA, US
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