Object-oriented domain specific compilers for programming FPGAs

Published versio

Intelligent systems engineering with reconfigurable computing

Intelligent computing systems comprising microprocessor cores, memory and reconfigurable user-programmable logic represent a promising technology which is well-suited for applications such as digital signal and image processing, cryptography and encryption, etc. These applications employ frequently recursive algorithms which are particularly appropriate when the underlying problem is defined in recursive terms and it is difficult to reformulate it as an iterative procedure. It is known, however, that hardware description languages (such as VHDL) as well as system-level specification languages (such as Handel-C) that are usually employed for specifying the required functionality of reconfigurable systems do not provide a direct support for recursion. In this paper a method allowing recursive algorithms to be easily described in Handel-C and implemented in an FPGA (field-programmable gate array) is proposed. The recursive search algorithm for the knapsack problem is considered as an exampleApplications in Artificial Intelligence - Knowledge EngineeringRed de Universidades con Carreras en Informática (RedUNCI

Solving graph coloring and SAT problems using field programmable gate arrays.

Chu-Keung Chung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1999.Includes bibliographical references (leaves 88-92).Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation and Aims --- p.1Chapter 1.2 --- Contributions --- p.3Chapter 1.3 --- Structure of the Thesis --- p.4Chapter 2 --- Literature Review --- p.6Chapter 2.1 --- Introduction --- p.6Chapter 2.2 --- Complete Algorithms --- p.7Chapter 2.2.1 --- Parallel Checking --- p.7Chapter 2.2.2 --- Mom's --- p.8Chapter 2.2.3 --- Davis-Putnam --- p.9Chapter 2.2.4 --- Nonchronological Backtracking --- p.9Chapter 2.2.5 --- Iterative Logic Array (ILA) --- p.10Chapter 2.3 --- Incomplete Algorithms --- p.11Chapter 2.3.1 --- GENET --- p.11Chapter 2.3.2 --- GSAT --- p.12Chapter 2.4 --- Summary --- p.13Chapter 3 --- Algorithms --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Tree Search Techniques --- p.14Chapter 3.2.1 --- Depth First Search --- p.15Chapter 3.2.2 --- Forward Checking --- p.16Chapter 3.2.3 --- Davis-Putnam --- p.17Chapter 3.2.4 --- GRASP --- p.19Chapter 3.3 --- Incomplete Algorithms --- p.20Chapter 3.3.1 --- GENET --- p.20Chapter 3.3.2 --- GSAT Algorithm --- p.22Chapter 3.4 --- Summary --- p.23Chapter 4 --- Field Programmable Gate Arrays --- p.24Chapter 4.1 --- Introduction --- p.24Chapter 4.2 --- FPGA --- p.24Chapter 4.2.1 --- Xilinx 4000 series FPGAs --- p.26Chapter 4.2.2 --- Bitstream --- p.31Chapter 4.3 --- Giga Operations Reconfigurable Computing Platform --- p.32Chapter 4.4 --- Annapolis Wildforce PCI board --- p.33Chapter 4.5 --- Summary --- p.35Chapter 5 --- Implementation --- p.36Chapter 5.1 --- Parallel Graph Coloring Machine --- p.36Chapter 5.1.1 --- System Architecture --- p.38Chapter 5.1.2 --- Evaluator --- p.39Chapter 5.1.3 --- Finite State Machine (FSM) --- p.42Chapter 5.1.4 --- Memory --- p.43Chapter 5.1.5 --- Hardware Resources --- p.43Chapter 5.2 --- Serial Graph Coloring Machine --- p.44Chapter 5.2.1 --- System Architecture --- p.44Chapter 5.2.2 --- Input Memory --- p.46Chapter 5.2.3 --- Solution Store --- p.46Chapter 5.2.4 --- Constraint Memory --- p.47Chapter 5.2.5 --- Evaluator --- p.48Chapter 5.2.6 --- Input Mapper --- p.49Chapter 5.2.7 --- Output Memory --- p.49Chapter 5.2.8 --- Backtrack Checker --- p.50Chapter 5.2.9 --- Word Generator --- p.51Chapter 5.2.10 --- State Machine --- p.51Chapter 5.2.11 --- Hardware Resources --- p.54Chapter 5.3 --- Serial Boolean Satisfiability Solver --- p.56Chapter 5.3.1 --- System Architecture --- p.58Chapter 5.3.2 --- Solutions --- p.59Chapter 5.3.3 --- Solution Generator --- p.59Chapter 5.3.4 --- Evaluator --- p.60Chapter 5.3.5 --- AND/OR --- p.62Chapter 5.3.6 --- State Machine --- p.62Chapter 5.3.7 --- Hardware Resources --- p.64Chapter 5.4 --- GSAT Solver --- p.65Chapter 5.4.1 --- System Architecture --- p.65Chapter 5.4.2 --- Variable Memory --- p.65Chapter 5.4.3 --- Flip-Bit Vector --- p.66Chapter 5.4.4 --- Clause Evaluator --- p.67Chapter 5.4.5 --- Adder --- p.70Chapter 5.4.6 --- Random Bit Generator --- p.71Chapter 5.4.7 --- Comparator --- p.71Chapter 5.4.8 --- Sum Register --- p.71Chapter 5.5 --- Summary --- p.71Chapter 6 --- Results --- p.73Chapter 6.1 --- Introduction --- p.73Chapter 6.2 --- Parallel Graph Coloring Machine --- p.73Chapter 6.3 --- Serial Graph Coloring Machine --- p.74Chapter 6.4 --- Serial SAT Solver --- p.74Chapter 6.5 --- GSAT Solver --- p.75Chapter 6.6 --- Summary --- p.76Chapter 7 --- Conclusion --- p.77Chapter 7.1 --- Future Work --- p.78Chapter A --- Software Implementation of Graph Coloring in CHIP --- p.79Chapter B --- Density Improvements Using Xilinx RAM --- p.81Chapter C --- Bit stream Configuration --- p.83Bibliography --- p.88Publications --- p.9

An O(n) time discrete relaxation architecture for real-time processing of the consistent labeling problem

technical reportDiscrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conventional hardware design for a Discrete Relaxation Algorithm (DRA) suffers from 0(n2m3 ) time complexity and Oinhn2) space complexity. By reformulating DRA into a parallel computational tree and using a multiple tree-root pipelining scheme, time complexity is reduced to O(nm), while the space complexity is reduced by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm). Furthermore, a technique for dynamic configuring an architectural wavefront is used which leads to an O(n) time highly configurable DRA3 architecture

Hardware Acceleration of Electronic Design Automation Algorithms

With the advances in very large scale integration (VLSI) technology, hardware is going parallel. Software, which was traditionally designed to execute on single core microprocessors, now faces the tough challenge of taking advantage of this parallelism, made available by the scaling of hardware. The work presented in this dissertation studies the acceleration of electronic design automation (EDA) software on several hardware platforms such as custom integrated circuits (ICs), field programmable gate arrays (FPGAs) and graphics processors. This dissertation concentrates on a subset of EDA algorithms which are heavily used in the VLSI design flow, and also have varying degrees of inherent parallelism in them. In particular, Boolean satisfiability, Monte Carlo based statistical static timing analysis, circuit simulation, fault simulation and fault table generation are explored. The architectural and performance tradeoffs of implementing the above applications on these alternative platforms (in comparison to their implementation on a single core microprocessor) are studied. In addition, this dissertation also presents an automated approach to accelerate uniprocessor code using a graphics processing unit (GPU). The key idea is to partition the software application into kernels in an automated fashion, such that multiple instances of these kernels, when executed in parallel on the GPU, can maximally benefit from the GPU?s hardware resources. The work presented in this dissertation demonstrates that several EDA algorithms can be successfully rearchitected to maximally harness their performance on alternative platforms such as custom designed ICs, FPGAs and graphic processors, and obtain speedups upto 800X. The approaches in this dissertation collectively aim to contribute towards enabling the computer aided design (CAD) community to accelerate EDA algorithms on arbitrary hardware platforms

Intelligent systems engineering with reconfigurable computing

Intelligent computing systems comprising microprocessor cores, memory and reconfigurable user-programmable logic represent a promising technology which is well-suited for applications such as digital signal and image processing, cryptography and encryption, etc. These applications employ frequently recursive algorithms which are particularly appropriate when the underlying problem is defined in recursive terms and it is difficult to reformulate it as an iterative procedure. It is known, however, that hardware description languages (such as VHDL) as well as system-level specification languages (such as Handel-C) that are usually employed for specifying the required functionality of reconfigurable systems do not provide a direct support for recursion. In this paper a method allowing recursive algorithms to be easily described in Handel-C and implemented in an FPGA (field-programmable gate array) is proposed. The recursive search algorithm for the knapsack problem is considered as an exampleApplications in Artificial Intelligence - Knowledge EngineeringRed de Universidades con Carreras en Informática (RedUNCI