TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.Fil: Jiang, Lanlan. Soochow University; ChinaFil: Shi, Yuanyuan. Soochow University; China. University of Stanford; Estados UnidosFil: Hui, Fei. Soochow University; China. Massachusetts Institute of Technology; Estados UnidosFil: Tang, Kechao. University of Stanford; Estados UnidosFil: Wu, Qian. Soochow University; ChinaFil: Pan, Chengbin. Soochow University; ChinaFil: Jing, Xu. Soochow University; China. University of Texas at Austin; Estados UnidosFil: Uppal, Hasan. University of Manchester; Reino UnidoFil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Lu, Guangyuan. Chinese Academy of Sciences; República de ChinaFil: Wu, Tianru. Chinese Academy of Sciences; República de ChinaFil: Wang, Haomin. Chinese Academy of Sciences; República de ChinaFil: Villena, Marco A.. Soochow University; ChinaFil: Xie, Xiaoming. Chinese Academy of Sciences; República de China. ShanghaiTech University; ChinaFil: McIntyre, Paul C.. University of Stanford; Estados UnidosFil: Lanza, Mario. Soochow University; Chin

Reliability modeling of ultra-thin gate oxide and high-k dielectrics for nano-scale CMOS devices

Ph.DDOCTOR OF PHILOSOPH

Yield and Reliability Analysis for Nanoelectronics

As technology has continued to advance and more break-through emerge, semiconductor devices with dimensions in nanometers have entered into all spheres of our lives. Accordingly, high reliability and high yield are very much a central concern to guarantee the advancement and utilization of nanoelectronic products. However, there appear to be some major challenges related to nanoelectronics in regard to the field of reliability: identification of the failure mechanisms, enhancement of the low yields of nano products, and management of the scarcity and secrecy of available data [34]. Therefore, this dissertation investigates four issues related to the yield and reliability of nanoelectronics. Yield and reliability of nanoelectronics are affected by defects generated in the manufacturing processes. An automatic method using model-based clustering has been developed to detect the defect clusters and identify their patterns where the distribution of the clustered defects is modeled by a new mixture distribution of multivariate normal distributions and principal curves. The new mixture model is capable of modeling defect clusters with amorphous, curvilinear, and linear patterns. We evaluate the proposed method using both simulated and experimental data and promising results have been obtained. Yield is one of the most important performance indexes for measuring the success of nano fabrication and manufacturing. Accurate yield estimation and prediction is essential for evaluating productivity and estimating production cost. This research studies advanced yield modeling approaches which consider the spatial variations of defects or defect counts. Results from real wafer map data show that the new yield models provide significant improvement in yield estimation compared to the traditional Poisson model and negative binomial model. The ultra-thin SiO2 is a major factor limiting the scaling of semiconductor devices. High-k gate dielectric materials such as HfO2 will replace SiO2 in future generations of MOS devices. This study investigates the two-step breakdown mechanisms and breakdown sequences of double-layered high-k gate stacks by monitoring the relaxation of the dielectric films. The hazard rate is a widely used metric for measuring the reliability of electronic products. This dissertation studies the hazard rate function of gate dielectrics breakdown. A physically feasible failure time distribution is used to model the time-to-breakdown data and a Bayesian approach is adopted in the statistical analysis

EXPERIMENTAL STUDY OF BIAS TEMPERATURE INSTABILITY AND PROGRESSIVE BREAKDOWN OF ADVANCED GATE DIELECTRICS

With shrinking gate dielectrics, the reliability requirements of semiconductor gate dielectrics become more and more difficult to maintain. New physical mechanisms and phenomena are discovered and new challenges arise. At the same time, some issues, which have been minor in the past, begin to show bigger impact, such as the Negative Bias Temperature Instability issue. The dynamic NBTI phenomenon was studied with ultrathin SiO2 and HfO2 devices. With a dynamic stress condition, the device lifetime can be largely extended due to the reduced NBTI degradation. This reduction is contributed to the annealing of fixed oxide charges during the stress off period. A mathematical model is also established to explain this phenomenon. With alternative gate dielectrics' introduction, new issues associated with these materials and device structures are also raised. Those issues need to be studied in detail before fully incorporation of new materials. Compared with SiO2 devices, the NBTI degradation of HfO2 has a similar trend. However, it is found that they have different frequency response than the SiO2 devices. This difference is later found due to the traps inside the gate dielectrics. Detailed studies show that NBTI degradations at dc stress and dynamic stress conditions have different temperature acceleration factors due to the bulk traps. The disappearance of this difference by insetting a detrapping period further proves this observation. As we enter the ultrathin gate dielectrics regime, the electron tunneling mechanisms behind the gate dielectrics breakdown shift. Consequently, gate dielectrics breakdown mode also shifts from the clear-detected hard breakdown to the noisy soft breakdown. Thus new lifetime extrapolation models are needed. The progressive breakdown of ultrathin SiO2 is studied by a two-step test methodology. By monitoring the degradation of the progressive breakdown path in terms of the activation energy, the voltage acceleration factor, two kinds of breakdown filaments, the stable one and the unstable one, were studied. The stable filament is found to be a breakdown filament independent of the original breakdown filament, and the unstable filament is the continuing degradation of the original filament

Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology

In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies. In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature. In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides. In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide. In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed. An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved