From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Secure Virtualization and Multicore Platforms State-of-the-Art report

SVaM

Semiconductor Manufacturing Basics, Comparison Between Agent Based and Discrete Event Simulation

El trabajo consta de dos partes principales, la descripción detallada y caracterización de la industria de los semiconductores entendida en el contexto del transporte de materiales, donde los procesos de fabricación requeridos para conseguir el producto final son tan numerosos que hacen obligatorio el uso de tecnologías de simulación con el fin de optimizar la eficiencia en tanto la fabricación como el almacenamiento. Posteriormente se centra en el dilema creado en los últimos años debido a la utilización de diferentes técnicas y enfoques de simulación, teniendo como objeto de estudio los enfoques Agent Based y Discrete Event realiza una detallada comparativa donde se exponen argumentos a favor y en contra de la utilización de cada uno de estos enfoques dependiendo del modelado que se deba realizar siendo finalmente el usuario quien toma la decisión última según el tipo de sistema que desee modelar.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería Mecánic

Hybrid Multiresolution Simulation & Model Checking: Network-On-Chip Systems

abstract: Designers employ a variety of modeling theories and methodologies to create functional models of discrete network systems. These dynamical models are evaluated using verification and validation techniques throughout incremental design stages. Models created for these systems should directly represent their growing complexity with respect to composition and heterogeneity. Similar to software engineering practices, incremental model design is required for complex system design. As a result, models at early increments are significantly simpler relative to real systems. While experimenting (verification or validation) on models at early increments are computationally less demanding, the results of these experiments are less trustworthy and less rewarding. At any increment of design, a set of tools and technique are required for controlling the complexity of models and experimentation. A complex system such as Network-on-Chip (NoC) may benefit from incremental design stages. Current design methods for NoC rely on multiple models developed using various modeling frameworks. It is useful to develop frameworks that can formalize the relationships among these models. Fine-grain models are derived using their coarse-grain counterparts. Moreover, validation and verification capability at various design stages enabled through disciplined model conversion is very beneficial. In this research, Multiresolution Modeling (MRM) is used for system level design of NoC. MRM aids in creating a family of models at different levels of scale and complexity with well-formed relationships. In addition, a variant of the Discrete Event System Specification (DEVS) formalism is proposed which supports model checking. Hierarchical models of Network-on-Chip components may be created at different resolutions while each model can be validated using discrete-event simulation and verified via state exploration. System property expressions are defined in the DEVS language and developed as Transducers which can be applied seamlessly for model checking and simulation purposes. Multiresolution Modeling with verification and validation capabilities of this framework complement one another. MRM manages the scale and complexity of models which in turn can reduces V&V time and effort and conversely the V&V helps ensure correctness of models at multiple resolutions. This framework is realized through extending the DEVS-Suite simulator and its applicability demonstrated for exemplar NoC models.Dissertation/ThesisDoctoral Dissertation Computer Science 201

Integrated design for integrated photonics: from the physical to the circuit level and back

Silicon photonics is maturing rapidly on a technology basis, but design challenges are still prevalent. We discuss these challenges and explain how design of photonic integrated circuits needs to be handled on both the circuit as on the physical level. We also present a number of tools based on the IPKISS design framework