5 research outputs found

    Using genetic evolutionary software application testing to verify a DSP SoC

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    Copyright © 2008 IEEEA digital signal processor (DSP) system-on-chip (SoC) can be designed using a variety of architectures and techniques. This often presents different verification challenges compared to conventional SoC or processor designs. Verification of such designs should take into account the goals and applications of the DSP, and how they are eventually used. This paper proposes an application based verification methodology and demonstrates this technique on a real-life DSP SoC design. Our technique employs a library of specially devised application functions as test building blocks, followed by a genetic evolutionary test generator to compose these application functions into effective test programs.Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Le

    A software test program generator for verifying system-on-chips

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    © 2005 IEEE.Design verification is crucial for successful systems-on-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a technique to test the SoC at the system level using software application based programs. Our software application level verification methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios.Cheng, A.; Cheng-Chew Lim; Parashkevov, A

    Exploiting Don\u27t Cares to Enhance Functional Tests

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    In simulation based design verification, deterministic or pseudo-random tests are used to check functional correctness of a design. In this paper we present a technique generating tests by specifying the don’t care inputs in the functional specifications so as to improve their coverage of both design errors and manufacturing faults. The don’t cares are chosen to maximize sensitization of signals in the circuit. The tests generated in this way require only a fraction of pseudo-exhaustive test patterns to achieve a high multiplicity of fault coverage

    Design and validation of a simultaneous multi-threaded DLX processor

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    technical reportModern day computer systems rely on two forms of parallelism to achieve high performance, parallelism between individual instructions of a program (ILP) and parallelism between individual threads (TLP). Superscalar processors exploit ILP by issuing several instructions per clock, and multiprocessors (MP) exploit TLP by running different threads in parallel on different processors. A fundamental imitation of these approaches to exploit parallelism is that processor resources are statically partitioned. If TLP is low, processors in a MP system will be idle, and if ILP is low, issue slots in a superscalar processor will be wasted. As a consequence, the hardware cannot adapt to changing levels of ILP and TLP and resource utilization tend to be low. Since resource utilization is low there is potential to achieve higher performance if somehow useful instructions could be found to fill up the wasted issue slots. This paper explores a method called simultaneous multithreading (SMT) that addresses the utilization problem by letting multiple threads compete for the resources of a single processor each clock cycle thus increasing the potential ILP available

    Code generation and analysis for the functional verification of micro processors

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