58 research outputs found

    Modelling and optimising micro-nozzle resin injection repair of impacted composites using CFD

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    Resin injection repair is identified to have a gap of knowledge and rigour in the modelling and execution of the process. We outline the strategy of our proposed predictive modelling strategy of ‘reconstruction-simulation-injection’ to simulate real cases to improve repair outcomes. We model the damage zone using Darcy’s law and determine permeability using two methods applied on the Kozeny-Carman equation. We then discuss how we evaluate porosity and detail two proposed methods on reconstructing the porosity field. We verify the model through simulation, and demonstrate verification using a novel comprehensive 2D porosity liquid-ideal gas phase flow model after deriving the analytical solution, which is a contribution of our work. Next, we apply the now-established model to reconstruct real damage cases using the two methods and compare them. We also calibrate the permeability parameter for the model by comparison to a simulation accuracy index, and also calibrate an ultrasonic scanning parameter to minimise reconstruction artefacts as well as the sensitivity of the reconstructed geometry characteristics to scan parameter variations. Then, we validate the model by simulating real repair cases and comparing them to the experimental outcomes, achieving simulation accuracy indices of about 70% or more. We demonstrate the application of the resin injection model by applying resin injection in a proof-of-concept simulation and use it for a case study, and examine the importance of hole configuration, vacuum usage as well as resin flow behaviour between inlet and outlet holes in the context of a given damage area geometry. It is important to maximise the total length of resin flow paths available, through carefully placing inlet and outlet holes, to allow resin to infiltrate the damage zone as much as possible. Vacuum increases the minimum achievable filling, and it is still invariably better to use vacuum with an optimal hole placement, instead of one or the other. In a second case study, we improve the predicted outcome by the model after intentionally changing the hole configuration to maximise resin infiltration, demonstrating that filling can be improved by placing holes intelligently (e.g. by using gathered information on the damage area, together with knowledge of how resin would flow). Using this, we conduct an optimisation study of the resin injection model by first setting up the optimisation strategy and carefully determining the methodology. The optimisation procedure is verified by using one and two degree-of-freedom optimisation cases, with known optima. Then, the optimisation strategy is applied to reconstructed repair cases to demonstrate and assess the efficacy of the optimisation procedure, with average reductions in unfilled volumes of approximately 28% compared to initial configurations.Open Acces

    Design Automation and Application for Emerging Reconfigurable Nanotechnologies

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    In the last few decades, two major phenomena have revolutionized the electronic industry – the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have been complementing each other in a way that while electronics, in general, have demanded more computations per functional unit, CMOS downscaling has aptly supported such needs. However, while the computational demand is still rising exponentially, CMOS downscaling is reaching its physical limits. Hence, the need to explore viable emerging nanotechnologies is more imperative than ever. This thesis focuses on streamlining the existing design automation techniques for a class of emerging reconfigurable nanotechnologies. Transistors based on this technology exhibit duality in conduction, i.e. they can be configured dynamically either as a p-type or an n-type device on the application of an external bias. Owing to this dynamic reconfiguration, these transistors are also referred to as Reconfigurable Field-Effect Transistors (RFETs). Exploring and developing new technologies just like CMOS, require tackling two main challenges – first, design automation flow has to be modified to enable tailor- made circuit designs. Second, possible application opportunities should be explored where such technologies can outsmart the existing CMOS technologies. This thesis targets the above two objectives for emerging reconfigurable nanotechnologies by proposing approaches for enabling an Electronic Design Automation (EDA) flow for circuits based on RFETs and exploring hardware security as an application that exploits the transistor-level dynamic reconfiguration offered by this technology. This thesis explains the bottom-up approach adopted to propose a logic synthesis flow by identifying new logic gates and circuit design paradigms that can particularly exploit the dynamic reconfiguration offered by these novel nanotechnologies. This led to the subsequent need of finding natural Boolean logic abstraction for emerging reconfigurable nanotechnologies as it is shown that the existing abstraction of negative unate logic for CMOS technologies is sub-optimal for RFETs-based circuits. In this direction, it has been shown that duality in Boolean logic is a natural abstraction for this technology and can truly represent the duality in conduction offered by individual transistors. Finding this abstraction paved the way for defining suitable primitives and proposing various algorithms for logic synthesis and technology mapping. The following step is to explore compatible physical synthesis flow for emerging reconfigurable nanotechnologies. Using silicon nanowire-based RFETs, .lef and .lib files have been provided which can provide an end-to-end flow to generate .GDSII file for circuits exclusively based on RFETs. Additionally, new approaches have been explored to improve placement and routing for circuits based on reconfigurable nanotechnologies. It has been demonstrated how these approaches led to superior results as compared to the native flow meant for CMOS. Lastly, the unique property of transistor-level reconfiguration offered by RFETs is utilized to implement efficient Intellectual Property (IP) protection schemes against adversarial attacks. The ability to control the conduction of individual transistors can be argued as one of the impactful features of this technology and suitably fits into the paradigm of security measures. Prior security schemes based on CMOS technology often come with large overheads in terms of area, power, and delay. In contrast, RFETs-based hardware security measures such as logic locking, split manufacturing, etc. proposed in this thesis, demonstrate affordable security solutions with low overheads. Overall, this thesis lays a strong foundation for the two main objectives – design automation, and hardware security as an application, to push emerging reconfigurable nanotechnologies for commercial integration. Additionally, contributions done in this thesis are made available under open-source licenses so as to foster new research directions and collaborations.:Abstract List of Figures List of Tables 1 Introduction 1.1 What are emerging reconfigurable nanotechnologies? 1.2 Why does this technology look so promising? 1.3 Electronics Design Automation 1.4 The game of see-saw: key challenges vs benefits for emerging reconfigurable nanotechnologies 1.4.1 Abstracting ambipolarity in logic gate designs 1.4.2 Enabling electronic design automation for RFETs 1.4.3 Enhanced functionality: a suitable fit for hardware security applications 1.5 Research questions 1.6 Entire RFET-centric EDA Flow 1.7 Key Contributions and Thesis Organization 2 Preliminaries 2.1 Reconfigurable Nanotechnology 2.1.1 1D devices 2.1.2 2D devices 2.1.3 Factors favoring circuit-flexibility 2.2 Feasibility aspects of RFET technology 2.3 Logic Synthesis Preliminaries 2.3.1 Circuit Model 2.3.2 Boolean Algebra 2.3.3 Monotone Function and the property of Unateness 2.3.4 Logic Representations 3 Exploring Circuit Design Topologies for RFETs 3.1 Contributions 3.2 Organization 3.3 Related Works 3.4 Exploring design topologies for combinational circuits: functionality-enhanced logic gates 3.4.1 List of Combinational Functionality-Enhanced Logic Gates based on RFETs 3.4.2 Estimation of gate delay using the logical effort theory 3.5 Invariable design of Inverters 3.6 Sequential Circuits 3.6.1 Dual edge-triggered TSPC-based D-flip flop 3.6.2 Exploiting RFET’s ambipolarity for metastability 3.7 Evaluations 3.7.1 Evaluation of combinational logic gates 3.7.2 Novel design of 1-bit ALU 3.7.3 Comparison of the sequential circuit with an equivalent CMOS-based design 3.8 Concluding remarks 4 Standard Cells and Technology Mapping 4.1 Contributions 4.2 Organization 4.3 Related Work 4.4 Standard cells based on RFETs 4.4.1 Interchangeable Pull-Up and Pull-Down Networks 4.4.2 Reconfigurable Truth-Table 4.5 Distilling standard cells 4.6 HOF-based Technology Mapping Flow for RFETs-based circuits 4.6.1 Area adjustments through inverter sharings 4.6.2 Technology Mapping Flow 4.6.3 Realizing Parameters For The Generic Library 4.6.4 Defining RFETs-based Genlib for HOF-based mapping 4.7 Experiments 4.7.1 Experiment 1: Distilling standard-cells from a benchmark suite 4.7.2 Experiment 2A: HOF-based mapping . 4.7.3 Experiment 2B: Using the distilled standard-cells during mapping 4.8 Concluding Remarks 5 Logic Synthesis with XOR-Majority Graphs 5.1 Contributions 5.2 Organization 5.3 Motivation 5.4 Background and Preliminaries 5.4.1 Terminologies 5.4.2 Self-duality in NPN classes 5.4.3 Majority logic synthesis 5.4.4 Earlier work on XMG 5.4.5 Classification of Boolean functions 5.5 Preserving Self-Duality 5.5.1 During logic synthesis 5.5.2 During versatile technology mapping 5.6 Advanced Logic synthesis techniques 5.6.1 XMG resubstitution 5.6.2 Exact XMG rewriting 5.7 Logic representation-agnostic Mapping 5.7.1 Versatile Mapper 5.7.2 Support of supergates 5.8 Creating Self-dual Benchmarks 5.9 Experiments 5.9.1 XMG-based Flow 5.9.2 Experimental Setup 5.9.3 Synthetic self-dual benchmarks 5.9.4 Cryptographic benchmark suite 5.10 Concluding remarks and future research directions 6 Physical synthesis flow and liberty generation 6.1 Contributions 6.2 Organization 6.3 Background and Related Work 6.3.1 Related Works 6.3.2 Motivation 6.4 Silicon Nanowire Reconfigurable Transistors 6.5 Layouts for Logic Gates 6.5.1 Layouts for Static Functional Logic Gates 6.5.2 Layout for Reconfigurable Logic Gate 6.6 Table Model for Silicon Nanowire RFETs 6.7 Exploring Approaches for Physical Synthesis 6.7.1 Using the Standard Place & Route Flow 6.7.2 Open-source Flow 6.7.3 Concept of Driver Cells 6.7.4 Native Approach 6.7.5 Island-based Approach 6.7.6 Utilization Factor 6.7.7 Placement of the Island on the Chip 6.8 Experiments 6.8.1 Preliminary comparison with CMOS technology 6.8.2 Evaluating different physical synthesis approaches 6.9 Results and discussions 6.9.1 Parameters Which Affect The Area 6.9.2 Use of Germanium Nanowires Channels 6.10 Concluding Remarks 7 Polymporphic Primitives for Hardware Security 7.1 Contributions 7.2 Organization 7.3 The Shift To Explore Emerging Technologies For Security 7.4 Background 7.4.1 IP protection schemes 7.4.2 Preliminaries 7.5 Security Promises 7.5.1 RFETs for logic locking (transistor-level locking) 7.5.2 RFETs for split manufacturing 7.6 Security Vulnerabilities 7.6.1 Realization of short-circuit and open-circuit scenarios in an RFET-based inverter 7.6.2 Circuit evaluation on sub-circuits 7.6.3 Reliability concerns: A consequence of short-circuit scenario 7.6.4 Implication of the proposed security vulnerability 7.7 Analytical Evaluation 7.7.1 Investigating the security promises 7.7.2 Investigating the security vulnerabilities 7.8 Concluding remarks and future research directions 8 Conclusion 8.1 Concluding Remarks 8.2 Directions for Future Work Appendices A Distilling standard-cells B RFETs-based Genlib C Layout Extraction File (.lef) for Silicon Nanowire-based RFET D Liberty (.lib) file for Silicon Nanowire-based RFET

    Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques

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    One key aspect to be considered during device testing is the minimization of the switching activity of the circuit under test (CUT), thus avoiding possible problems stemming from overheating it. But there are also scenarios, where the maximization of certain circuits' modules switching activity could be proven useful (e.g., during Burn-In) in order to exercise the circuit under extreme operating conditions in terms of temperature (and temperature gradients). Resorting to a functional approach based on Software-based Self-test guarantees that the high induced activity cannot damage the CUT nor produce any yield loss. However, the generation of effective suitable test programs remains a challenging task. In this paper, we consider a scenario where the modules to be stressed are sub-modules of a fully pipelined processor. We present a technique, based on an evolutionary approach, able to automatically generate stress test programs, i.e., sequences of instructions achieving a high toggling activity in the target module. With respect to previous approaches, the generated sequences are short and repeatable, thus guaranteeing their easy usability to stress a module (and increase its temperature). The processor we used for our experiments is the Open RISC 1200. Results demonstrate that the proposed method is effective in achieving a high value of sustained toggling activity with short (3 instructions) and repeatable sequences

    Network-on-Chip

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    Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

    Numerical simulations of real-gas flows with phase-equilibrium thermodynamics

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    Motivated by the complex physics of multi-component mixtures in strongly non-ideal, real-gas (RG) conditions reported in the field of chemical engineering, this work aims to address the behavior of multi-phase thermodynamics from a broader point of view. The focus is to evaluate the differences, as well as the possible sources of errors that would arise in a computational fluid-dynamics (CFD) simulation when conventional single-phase and multi-phase equilibrium RG thermodynamics are employed: an area of research that despite the active interest in many communities (especially CFD), has not been completely understood. Knowledge of the effects that multi-phase RG thermodynamics with the assumption of vapor-liquid equilibrium (VLE) can have on a flow dynamics is important because it establishes the relevance of the fully coupled CFD-VLE solver. In fact, this relevance may go beyond the stand-alone calculation of a multi-phase state, providing important insights about the physics that may not be captured if the single-phase assumption is invoked. This work provides an extensive study of RG mixtures from a physical and numerical point of view. The difficulties associated with their modeling are discussed in detail and solutions are provided accordingly. Emphasis is given to the occurrence and suppression of numerical noise in form of pressure oscillations that can pollute the simulation to the point that it cannot be performed. Extension of existing models to eliminate such problem is achieved by incorporating the effects of VLE thermodynamics in a consistent manner, ultimately forming a new and robust tool to investigate the physics further. The resulting model is applied to non-reacting and reacting flows in canonical setups where emphasis is devoted to the discussion of the differences and sources of errors that would occur if this multi-phase behavior is not taken into account. Results show that the different thermodynamic states reached by this advanced model can have an impact on the flow physics, especially in a non-reacting (or more in general cold) regime. In particular, the strong non-linear coupling between the VLE thermodynamics and the transport properties is identified as a key element of difference with respect to the single-phase model counterpart. These differences manifest into the occurrence of localized changes in the fluid properties (such as density) that affect the flow-field in their vicinity, causing visible discrepancies even when time-averaging is performed. Concurrently, results obtained on the reacting side and carried out (for the first time) with finite-rate kinetics suggest that any VLE formation between the products and the reactants may be considered of minor importance. The latter conclusion is supported by the analysis conducted on the multi-phase field which appears to be largely composed of the vapor solution, as expected, hence limiting the analogous effect observed the non-reacting system where a broader range of phase-separation appears instead.Ph.D

    REDUCING POWER DURING MANUFACTURING TEST USING DIFFERENT ARCHITECTURES

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    Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test. In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We group the control bits together into one or more control chains. To address the extra pin(s) required to shift data into the control chain(s) and significant post processing in the first architecture, we explored a second architecture. The second architecture stitches the control bits into the chains they control as EECBs (embedded enable capture bits) in between the segments. This allows an ATPG software tool to automatically generate the appropriate EECB values for each pattern to maintain the fault coverage. This also works in the presence of an on-chip decompressor. The last architecture focuses primarily on the self-test of a device in a 3D stacked IC when an existing FPGA in the stack can be programmed as a tester. We show that the energy expended during test is significantly less than would be required using low power patterns fed by an on-chip decompressor for the same very short scan chains

    Catalyst and reactor design for carbon dioxide methanation

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    [eng] The transformation of the current energy model towards a more sustainable mix, independent of fossil fuels, requires the exploration of new technologies that are capable of taking advantage of excess electricity derived from renewable energy sources and to use new alternative sources of carbon for the generation of clean fuels. An alternative that combines both is the Power-to-Gas (P2G) technology, whose concept is based on a two-stage process. In the first stage, excess electricity from renewable energies is converted to hydrogen by electrolysis. Then, in a second stage, the H2 produced is transformed to CH4 through methanation with CO2. The CH4 produced is referred to as synthetic natural gas (SNG) and allows large amounts of renewable energy to be distributed from the energy sector to the end-use sectors. The thermo-chemical CO2 methanation process is considered the most efficient route for large-scale SNG production. However, developing a cost-effective CO2 methanation technology is one of the biggest challenges facing the P2G concept. In this context, this thesis focused on the catalyst and reactor design for CO2 methanation. The thesis objectives were addressed in three main aspects, which are: i) design a high-performance catalyst based on metal oxide-promoted Ni/γ-Al2O3 and determine its reaction mechanism; ii) evaluate the stability of the catalyst and the tolerance to sulfur for its implementation in a relevant industrial environment (CoSin project); and finally, iii) develop a CFD model based on experimental kinetic data to understand the role of operating conditions and propose a new reactor configuration. In the first Chapter of this thesis it is presented a general introduction of the SNG production through CO2 methanation process. In the second Chapter, the addition of a promoter (X) on a system composed by Ni and γ-Al2O3 microspheres was studied as the design strategy to develop a micro-sized Ni-X/γ-Al2O3 catalyst. The catalysts based on Ni-CeO2/γ-Al2O3 was proposed as the most feasible due to its high catalytic performance in relation to its economic competitiveness. The optimal composition of each component of the Ni-CeO2/γ-Al2O3 was found through a systematic experimental design. The catalyst composed by 25wt.%Ni, 20wt.%CeO2 and 55wt.%γ-Al2O3 proved to be the most active and stable thanks to its enhanced Ni dispersion and reduction, its high metallic area, and the formation of moderate base sites. In Chapter three, the thermal stability and tolerance to sulfur impurities on the Ni-CeO2/γ-Al2O3 catalyst was further studied using high temperatures and the presence of H2S on the reactants. The strong metal-promoter interaction and the favourable formation of Ce2O2S were revealed as the main causes of its high stability and tolerance to H2S, respectively. Additionally, the implementation of Ni-CeO2/γ-Al2O3 in a two-stage industrial methanation process was performed to evaluate its technical feasibility. The desired gas composition (≥92.5%CH4) was successful obtained using a decreasing temperature profile (T=450-275°C) and P=5bar·g. The high stability recorded during the 2000h of experimentation demonstrated that Ni-CeO2/γ-Al2O3 can be a competitive catalyst for CO2 methanation. Regarding to reactor design, in Chapter four, the design of a fixed-bed multitubular reactor on a Ni-CeO2-Al2O3 catalyst was evaluated for mid-scale SNG production. A CFD mathematical model based on experimental kinetic data was developed. A reactor tube with a diameter of 9.25mm and a length of 250mm was proposed, which should be operated at Tinlet=473K, Twall=373K, GHSV=14,400h-1 and P=5atm to achieve XCO2=99% with Tmax of 673K. On the other hand, a reactor tube (di=4.6mm and L=250mm) with a heat management approach based on free convection was proposed for small-scale SNG production. The optimal conditions were found at GHSV=11,520h-1, Tinlet=503K, P=5atm, and Tair=298K. The feasibility of the simulated reactor proposal was experimentally validated over the micro-sized Ni-CeO2/γ-Al2O3 (XCO2=93% and T=830-495K).[spa] Power-to-Gas (P2G) es una tecnología prometedora para el almacenamiento de combustibles bajos en carbono. El concepto P2G implica la conversión de energía renovable en hidrógeno mediante electrólisis con la posibilidad de combinarlo con CO2 para producir metano (gas natural sintético, SNG). La producción de SNG mediante el proceso termoquímico de metanación de CO2 es particularmente interesante porque ofrece un combustible fácilmente transportable con un amplio mercado probado para aplicaciones de uso final de energía, calor y movilidad. Sin embargo, el desarrollo de una tecnología de metanación de CO2 rentable es uno de los mayores desafíos que enfrenta el concepto P2G. En este contexto, esta tesis se centró en el desarrollo de un catalizador y un reactor para la metanación de CO2. Los objetivos de la tesis se abordaron en tres aspectos principales, que son: i) diseñar un catalizador de alto rendimiento basado en Ni/The transformation of the current energy model towards a more sustainable mix, independent of fossil fuels, requires the exploration of new technologies that are capable of taking advantage of excess electricity derived from renewable energy sources and to use new alternative sources of carbon for the generation of clean fuels. An alternative that combines both is the Power-to-Gas (P2G) technology, whose concept is based on a two-stage process. In the first stage, excess electricity from renewable energies is converted to hydrogen by electrolysis. Then, in a second stage, the H2 produced is transformed to CH4 through methanation with CO2. The CH4 produced is referred to as synthetic natural gas (SNG) and allows large amounts of renewable energy to be distributed from the energy sector to the end-use sectors. The thermo-chemical CO2 methanation process is considered the most efficient route for large-scale SNG production. However, developing a cost-effective CO2 methanation technology is one of the biggest challenges facing the P2G concept. In this context, this thesis focused on the catalyst and reactor design for CO2 methanation. The thesis objectives were addressed in three main aspects, which are: i) design a high-performance catalyst based on metal oxide-promoted Ni/γ-Al2O3 and determine its reaction mechanism; ii) evaluate the stability of the catalyst and the tolerance to sulfur for its implementation in a relevant industrial environment (CoSin project); and finally, iii) develop a CFD model based on experimental kinetic data to understand the role of operating conditions and propose a new reactor configuration. In the first Chapter of this thesis it is presented a general introduction of the SNG production through CO2 methanation process. In the second Chapter, the addition of a promoter (X) on a system composed by Ni and γ-Al2O3 microspheres was studied as the design strategy to develop a micro-sized Ni-X/γ-Al2O3 catalyst. The catalysts based on Ni-CeO2/γ-Al2O3 was proposed as the most feasible due to its high catalytic performance in relation to its economic competitiveness. The optimal composition of each component of the Ni-CeO2/γ-Al2O3 was found through a systematic experimental design. The catalyst composed by 25wt.%Ni, 20wt.%CeO2 and 55wt.%γ-Al2O3 proved to be the most active and stable thanks to its enhanced Ni dispersion and reduction, its high metallic area, and the formation of moderate base sites. In Chapter three, the thermal stability and tolerance to sulfur impurities on the Ni-CeO2/γ-Al2O3 catalyst was further studied using high temperatures and the presence of H2S on the reactants. The strong metal-promoter interaction and the favourable formation of Ce2O2S were revealed as the main causes of its high stability and tolerance to H2S, respectively. Additionally, the implementation of Ni-CeO2/γ-Al2O3 in a two-stage industrial methanation process was performed to evaluate its technical feasibility. The desired gas composition (≥92.5%CH4) was successful obtained using a decreasing temperature profile (T=450-275°C) and P=5bar·g. The high stability recorded during the 2000h of experimentation demonstrated that Ni-CeO2/γ-Al2O3 can be a competitive catalyst for CO2 methanation. Regarding to reactor design, in Chapter four, the design of a fixed-bed multitubular reactor on a Ni-CeO2-Al2O3 catalyst was evaluated for mid-scale SNG production. A CFD mathematical model based on experimental kinetic data was developed. A reactor tube with a diameter of 9.25mm and a length of 250mm was proposed, which should be operated at Tinlet=473K, Twall=373K, GHSV=14,400h-1 and P=5atm to achieve XCO2=99% with Tmax of 673K. On the other hand, a reactor tube (di=4.6mm and L=250mm) with a heat management approach based on free convection was proposed for small-scale SNG production. The optimal conditions were found at GHSV=11,520h-1, Tinlet=503K, P=5atm, and Tair=298K. The feasibility of the simulated reactor proposal was experimentally validated over the micro-sized Ni-CeO2/γ-Al2O3 (XCO2=93% and T=830-495K).-Al2O3 promovido por óxido metálico y determinar su mecanismo, ii) evaluar la estabilidad del catalizador y la tolerancia al azufre para su implementación en un entorno industrial relevante (proyecto CoSin), and iii) desarrollar un modelo CFD basado en datos cinéticos experimentales para comprender el papel de las condiciones de operación y proponer una nueva configuración de reactor. En línea con estos objetivos, un catalizador ternario basado en 25wt.%Ni-20wt.%CeO2-55wt.%The transformation of the current energy model towards a more sustainable mix, independent of fossil fuels, requires the exploration of new technologies that are capable of taking advantage of excess electricity derived from renewable energy sources and to use new alternative sources of carbon for the generation of clean fuels. An alternative that combines both is the Power-to-Gas (P2G) technology, whose concept is based on a two-stage process. In the first stage, excess electricity from renewable energies is converted to hydrogen by electrolysis. Then, in a second stage, the H2 produced is transformed to CH4 through methanation with CO2. The CH4 produced is referred to as synthetic natural gas (SNG) and allows large amounts of renewable energy to be distributed from the energy sector to the end-use sectors. The thermo-chemical CO2 methanation process is considered the most efficient route for large-scale SNG production. However, developing a cost-effective CO2 methanation technology is one of the biggest challenges facing the P2G concept. In this context, this thesis focused on the catalyst and reactor design for CO2 methanation. The thesis objectives were addressed in three main aspects, which are: i) design a high-performance catalyst based on metal oxide-promoted Ni/γ-Al2O3 and determine its reaction mechanism; ii) evaluate the stability of the catalyst and the tolerance to sulfur for its implementation in a relevant industrial environment (CoSin project); and finally, iii) develop a CFD model based on experimental kinetic data to understand the role of operating conditions and propose a new reactor configuration. In the first Chapter of this thesis it is presented a general introduction of the SNG production through CO2 methanation process. In the second Chapter, the addition of a promoter (X) on a system composed by Ni and γ-Al2O3 microspheres was studied as the design strategy to develop a micro-sized Ni-X/γ-Al2O3 catalyst. The catalysts based on Ni-CeO2/γ-Al2O3 was proposed as the most feasible due to its high catalytic performance in relation to its economic competitiveness. The optimal composition of each component of the Ni-CeO2/γ-Al2O3 was found through a systematic experimental design. The catalyst composed by 25wt.%Ni, 20wt.%CeO2 and 55wt.%γ-Al2O3 proved to be the most active and stable thanks to its enhanced Ni dispersion and reduction, its high metallic area, and the formation of moderate base sites. In Chapter three, the thermal stability and tolerance to sulfur impurities on the Ni-CeO2/γ-Al2O3 catalyst was further studied using high temperatures and the presence of H2S on the reactants. The strong metal-promoter interaction and the favourable formation of Ce2O2S were revealed as the main causes of its high stability and tolerance to H2S, respectively. Additionally, the implementation of Ni-CeO2/γ-Al2O3 in a two-stage industrial methanation process was performed to evaluate its technical feasibility. The desired gas composition (≥92.5%CH4) was successful obtained using a decreasing temperature profile (T=450-275°C) and P=5bar·g. The high stability recorded during the 2000h of experimentation demonstrated that Ni-CeO2/γ-Al2O3 can be a competitive catalyst for CO2 methanation. Regarding to reactor design, in Chapter four, the design of a fixed-bed multitubular reactor on a Ni-CeO2-Al2O3 catalyst was evaluated for mid-scale SNG production. A CFD mathematical model based on experimental kinetic data was developed. A reactor tube with a diameter of 9.25mm and a length of 250mm was proposed, which should be operated at Tinlet=473K, Twall=373K, GHSV=14,400h-1 and P=5atm to achieve XCO2=99% with Tmax of 673K. On the other hand, a reactor tube (di=4.6mm and L=250mm) with a heat management approach based on free convection was proposed for small-scale SNG production. The optimal conditions were found at GHSV=11,520h-1, Tinlet=503K, P=5atm, and Tair=298K. The feasibility of the simulated reactor proposal was experimentally validated over the micro-sized Ni-CeO2/γ-Al2O3 (XCO2=93% and T=830-495K).-Al2O3 se propone como el más factible debido a su alto rendimiento catalítico en relación a su competitividad económica. La fuerte interacción metal-promotor y la formación favorable de Ce2O2S se revelaron como las principales causas de su alta estabilidad y tolerancia al H2S, respectivamente. Adicionalmente, su exitosa implementación en un proceso de metanación industrial de dos etapas demostró su viabilidad técnica. Finalmente, se propone un reactor multitubular para la producción de SNG a mediana escala. Por otro lado, para la producción de SNG a pequeña escala, se propone un nuevo diseño de reactor con un enfoque de gestión del calor basado en la libre convención

    A Holistic Solution for Reliability of 3D Parallel Systems

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    As device scaling slows down, emerging technologies such as 3D integration and carbon nanotube field-effect transistors are among the most promising solutions to increase device density and performance. These emerging technologies offer shorter interconnects, higher performance, and lower power. However, higher levels of operating temperatures and current densities project significantly higher failure rates. Moreover, due to the infancy of the manufacturing process, high variation, and defect densities, chip designers are not encouraged to consider these emerging technologies as a stand-alone replacement for Silicon-based transistors. The goal of this dissertation is to introduce new architectural and circuit techniques that can work around high-fault rates in the emerging 3D technologies, improving performance and reliability comparable to Silicon. We propose a new holistic approach to the reliability problem that addresses the necessary aspects of an effective solution such as detection, diagnosis, repair, and prevention synergically for a practical solution. By leveraging 3D fabric layouts, it proposes the underlying architecture to efficiently repair the system in the presence of faults. This thesis presents a fault detection scheme by re-executing instructions on idle identical units that distinguishes between transient and permanent faults while localizing it to the granularity of a pipeline stage. Furthermore, with the use of a dynamic and adaptive reconfiguration policy based on activity factors and temperature variation, we propose a framework that delivers a significant improvement in lifetime management to prevent faults due to aging. Finally, a design framework that can be used for large-scale chip production while mitigating yield and variation failures to bring up Carbon Nano Tube-based technology is presented. The proposed framework is capable of efficiently supporting high-variation technologies by providing protection against manufacturing defects at different granularities: module and pipeline-stage levels.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/168118/1/javadb_1.pd

    Synthesis of variability-tolerant circuits with adaptive clocking

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    Improvements in circuit manufacturing have allowed, along the years, increasingly complex designs. This has been enabled by the miniaturization that circuit components have undergone. But, in recent years, this scaling has shown decreasing benefits as we approach fundamental limits. Furthermore, the decrease in size is nowadays producing an increase in variability: unpredictable differences and changes in the behavior of components. Historically, this has been addressed by establishing guardband margins at the design stage. Nonetheless, as variability grows, the amount of pessimism introduced by these margins is taking an ever-increasing cost on performance and power consumption. In recent years, several approaches have been proposed to lower the impact of variability and reduce margins. One such technique is the substitution of a classical PLL clock by a Ring Oscillator Clock. The design of the Ring Oscillator Clock is done in such a way that its variability is highly correlated to that of the circuit. One of the contributions of this thesis is in the automatic design of such circuits. In particular, we propose a novel method to design digital delay lines with variability-tracking properties. Those designs are also suitable for other purposes, such as bundled-data circuits or performance monitors. The advantage of the proposed technique is based on the exclusive use of cells from a standard cell library, which lowers the design cost and complexity. The other focus of this thesis is on state encoding for asynchronous controllers. One of the main properties of asynchronous circuits is their ability to, implicitly, work under variable conditions. In the near future, this advantage might increase the relevance of this class of circuits. One of the hardest stages for the synthesis of these circuits is the state encoding. This thesis presents a SAT-based algorithm for solving the state encoding at the state level. It is shown, by means of a comprehensive benchmark suite, that results obtained by this technique improve significantly compared to results from similar approaches. Nonetheless, the main limitation of techniques at the state level is the state explosion problem, to which the sequential modeling of concurrency is often subject to. The last contribution of this thesis is a method to process asynchronous circuits in order to allow the use of state-based techniques for large instances. In particular, the process is divided into three stages: projection, signal insertion and re-composition. In the projection step, the behavior of the controller is simplified until the signal insertion can be performed by state-based techniques. Afterwards, the re-composition generalizes the insertion of the signal into the original controller. Experimental results show that this process enables the resolution of large controllers, in the order of 10 6 states, by state-based techniques. At the same time, only a minor impact in solution quality is observed, preserving one of the main advantages for state-based approaches.A lo largo de los años, mejoras en la fabricación de circuitos han permitido diseños cada vez más complejos. Esta tendencia, que ha tenido lugar gracias a la miniaturización de los componentes que forman estos circuitos, recientemente está mostrando beneficios decrecientes a medida que nos acercamos a ciertas limitaciones fundamentales. Además de estos beneficios decrecientes, la reducción en tamaño está produciendo un aumento, cada vez mayor, en la variabilidad: diferencias impredecibles y cambios en el comportamiento de los componentes. Esto se ha compensado históricamente con el uso de márgenes de seguridad en la fase de diseño. No obstante, a medida que la variabilidad crece, la cantidad de pesimismo que estos márgenes introducen está afectando significativamente el coste en rendimiento y consumo energético. En los últimos años se han propuesto diferentes técnicas para limitar el impacto de la variabilidad y reducir márgenes de seguridad. Una de estas técnicas consiste en substituir un reloj PLL clásico por un Ring Oscillator Clock. El diseño de un Ring Oscillator Clock se realiza de manera que su variabilidad este altamente correlacionada con la del circuito. Una de las contribuciones de esta tesis consiste en el diseño automático de estos relojes. Concretamente, se propone un nuevo método para diseñar líneas de retardo digitales (digital delay lines) que tengan como propiedad la capacidad de imitar la variabilidad de un circuito dado. Estos diseños son también apropiados para otros propósitos, tal y como circuitos con ?bundled-data? o monitorizadores de rendimiento. La ventaja del método propuesto con respecto a otras técnicas similares radica en el uso exclusivo de celdas provenientes de una librería de celdas estándar, lo que reduce considerablemente el coste de diseño y su complejidad. Por otro lado, esta tesis también se centra en la codificación de estados de circuitos asíncronos. Una de las principales propiedades de estos circuitos reside en su capacidad implícita para trabajar bajo condiciones de variabilidad. Es previsible que, en un futuro próximo, esta ventaja se vuelva aún más relevante. La síntesis de circuitos asíncronos consta de varias etapas, una de las cuales es la codificación de estados. Este trabajo presenta un algoritmo basado en SAT que permite resolver la codificación de estados a nivel de estado. Mediante el uso de un exhaustivo banco de pruebas, esta tesis muestra como resultados obtenidos por esta técnica mejoran significativamente en comparación con otros métodos similares. A pesar de ello, técnicas que trabajan a nivel de estado tienen como principal limitación el problema conocido como "explosión de estados" que aparece habitualmente cuando se modelan elementos concurrentes de manera secuencial. Así pues, la última contribución de esta tesis es la propuesta de un método para procesar circuitos asíncronos de manera que técnicas a nivel de estado sean usables para instancias grandes. En concreto, el proceso está dividido en tres fases: proyección, inserción de señal y re-composición. En la etapa de proyección, el comportamiento del controlador es simplificado suficientemente como para que la inserción de la señal se pueda realizar con técnicas a nivel de estado. A continuación, la re-composición generaliza esta inserción en el controlador original. Resultados experimentales muestran que este proceso permite la resolución de grandes controladores, del orden de 10^6 estados, mediante el uso de técnicas a nivel de estado. Al mismo tiempo, solo se observa un impacto mínimo en la calidad de las soluciones, preservando una de las mayores ventajas de los métodos a nivel de estado
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